参数资料
型号: MAX15002ATL+
厂商: Maxim Integrated Products
文件页数: 23/29页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM 40-TQFNEP
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 50
PWM 型: 电压模式
输出数: 2
频率 - 最大: 2.2MHz
电源电压: 5.5 V ~ 23 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 125°C
封装/外壳: 40-WFQFN 裸露焊盘
包装: 管件
MAX15002
Dual-Output Buck Controller with
Tracking/Sequencing
5) The gain of the modulator (Gain MOD )—comprised
of the regulator’s pulse-width modulator, LC filter,
feedback divider, and associated circuitry —at
crossover frequency is:
If a ceramic capacitor is used, the capacitor ESR
zero, f ESR , is likely to be located even above one-
half of the switching frequency, that is f LC < f CO <
f SW /2 < f ESR . In this case, the frequency of the sec-
ond pole (f P2 ) should be placed high enough not to
Gain MOD = 4 ×
1
( 2 π × f CO ) 2 × L × C OUT
significantly erode the phase margin at the
crossover frequency. For example, it can be set at 5
x f CO , so that its contribution to phase loss at the
The gain of the error amplifier (Gain E/A ) in midband fre-
quencies is:
Gain E/A = 2 π x f CO x C I x R F
crossover frequency f CO is only about 11°:
f P2 = 5 x f CO
Once f P2 is known, calculate R I :
The total loop gain as the product of the modulator gain
and the error-amplifier gain at f CO should be equal to 1,
as follows:
R I =
1
2 π × f P 2 × C I
So :
Gain MOD × Gain E A = 1
7) Place the second zero (f Z2 ) at 0.2 x f CO or at f LC ,
whichever is lower and calculate R 1 using the fol-
lowing equation:
( 2 π × f CO OUT × L
) × C
4 ×
2
1
× 2 π × f CO × C I × R F = 1
R 1 =
1
2 π × f Z 2 × C I
? R I
( 2 π × f CO × L × C OUT )
4 × R F
C CF =
Solving fo r C I :
C I =
6) For those situations where f LC < f CO < f ESR <
f SW /2—as with low-ESR tantalum capacitors—the
compensator’s second pole (f P2 ) should be used to
cancel f ESR . This provides additional phase margin.
8) Place the third pole (f P3 ) at 1/2 the switching fre-
quency and calculate C CF from:
1
2 π × 0 . 5 × f SW × R F
9) Calculate R 2 as:
Viewed mathematically on the system Bode plot, the
loop gain plot maintains its +20dB/dec slope up to
1/2 of the switching frequency verses flattening out
soon after the 0dB crossover. Then set:
f P2 = f ESR
Maxim Integrated
R 2 = R 1 ×
where V FB = 0.6V.
V FB
V OUT ? V FB
23
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