参数资料
型号: MAX15002ATL+
厂商: Maxim Integrated Products
文件页数: 22/29页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM 40-TQFNEP
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 50
PWM 型: 电压模式
输出数: 2
频率 - 最大: 2.2MHz
电源电压: 5.5 V ~ 23 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 125°C
封装/外壳: 40-WFQFN 裸露焊盘
包装: 管件
MAX15002
Dual-Output Buck Controller with
Tracking/Sequencing
Type III: Compensation when f CO < f ESR
As indicated above, the position of the output capaci-
tor’s inherent ESR zero is critical in designing an appro-
priate compensation network. When low-ESR ceramic
output capacitors are used, the ESR zero frequency
(f ESR ) is usually much higher than unity crossover fre-
Two midband zeros (f Z1 and f Z2 ) are designed to can-
cel the pair of complex poles introduced by the LC filter.
f P1 = at the origin (0Hz)
f P1 introduces a pole at zero frequency (integrator) for
nulling DC output-voltage errors.
quency (f CO ). In this case, a Type III compensation net-
work is recommended (see Figure 7a).
f P 2 =
1
2 π × R I × C I
V OUT
C CF
Depending on the location of the ESR zero (f ESR ), f P2
can be used to cancel it, or to provide additional atten-
R I
R 1
R F
C F
uation of the high-frequency output ripple.
C I
R 2
FB
V REF
-
g m
+
COMP
f P 3 =
1
2 π × R F × ( C F || C CF )
=
2 π × R F ×
1
C F × C CF
C F + C CF
f P3 attenuates the high-frequency output ripple.
The locations of the zeros and poles should be such
Figure 7a. Type III Compensation Network
GAIN
that the phase margin peaks around f CO .
Set the ratios of f CO -to-f Z and f P -to-f CO equal to one
another, e.g., f CO = f P = 5 is a good number to get about
(dB)
f Z
f CO
60° of phase margin at f CO . Whichever technique, it is
4TH ASYMPTOTE
R F R I
important to place the two zeros at or below the double
pole to avoid the conditional stability issue.
f CO ≤ SW
3RD ASYMPTOTE
ω R F C I
1ST ASYMPTOTE
ω R I C F-1
2ND ASYMPTOTE
R F R I-1
5TH ASYMPTOTE
ω R I C CF-1
The following procedure is recommended:
1) Select a crossover frequency, f CO , at or below one-
tenth the switching frequency:
f
10
1ST POLE
(AT ORIGIN)
1ST ZERO
R F C F
2ND POLE
R I C I
3RD POLE ω (rad/sec)
R F C CF
2) Calculate the LC double-pole frequency, f LC :
2ND ZERO
R I C I
Figure 7b. Type III Compensation Network Response
f LC =
1
2 π× L × COUT
As shown in Figure 7b, the Type III compensation net-
work introduces two zeros and three poles into the con-
trol loop. The error amplifier has a low-frequency pole
at the origin, two zeros, and two higher frequency poles
3) Select R F ≥ 10k ? .
4) Place compensator ’s first zero f Z 1 =
at or below the output filter ’s
double pole, f LC , as follows:
1
2 π × R F × C F
f Z 1 =
at the following frequencies:
1
2 π × R F × C F
C F =
1
2 π × R F × 0 . 5 × f LC
22
f Z 2 =
1
2 π × C I × ( R 1 + R I )
Maxim Integrated
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