参数资料
型号: ATTINY13V-10SSUR
厂商: Atmel
文件页数: 24/176页
文件大小: 0K
描述: MCU AVR 1KB FLASH 10MHZ 8SOIC
产品培训模块: tinyAVR Introduction
标准包装: 4,000
系列: AVR® ATtiny
核心处理器: AVR
芯体尺寸: 8-位
速度: 10MHz
外围设备: 欠压检测/复位,POR,PWM,WDT
输入/输出数: 6
程序存储器容量: 1KB(512 x 16)
程序存储器类型: 闪存
EEPROM 大小: 64 x 8
RAM 容量: 64 x 8
电压 - 电源 (Vcc/Vdd): 1.8 V ~ 5.5 V
数据转换器: A/D 4x10b
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 8-SOIC(0.154",3.90mm 宽)
包装: 带卷 (TR)
其它名称: ATTINY13V-10SSUR-ND
ATTINY13V-10SSURTR
12
2535J–AVR–08/10
ATtiny13
4.6
Instruction Execution Timing
This section describes the general access timing concepts for instruction execution. The AVR
CPU is driven by the CPU clock clkCPU, directly generated from the selected clock source for the
chip. No internal clock division is used.
Figure 4-4 on page 12 shows the parallel instruction fetches and instruction executions enabled
by the Harvard architecture and the fast access Register File concept. This is the basic pipelin-
ing concept to obtain up to 1 MIPS per MHz with the corresponding unique results for functions
per cost, functions per clocks, and functions per power-unit.
Figure 4-4.
The Parallel Instruction Fetches and Instruction Executions
Figure 4-5 on page 12 shows the internal timing concept for the Register File. In a single clock
cycle an ALU operation using two register operands is executed, and the result is stored back to
the destination register.
Figure 4-5.
Single Cycle ALU Operation
4.7
Reset and Interrupt Handling
The AVR provides several different interrupt sources. These interrupts and the separate Reset
Vector each have a separate Program Vector in the Program memory space. All interrupts are
assigned individual enable bits which must be written logic one together with the Global Interrupt
Enable bit in the Status Register in order to enable the interrupt.
The lowest addresses in the Program memory space are by default defined as the Reset and
Interrupt Vectors. The complete list of vectors is shown in “Interrupts” on page 44. The list also
determines the priority levels of the different interrupts. The lower the address the higher is the
clk
1st Instruction Fetch
1st Instruction Execute
2nd Instruction Fetch
2nd Instruction Execute
3rd Instruction Fetch
3rd Instruction Execute
4th Instruction Fetch
T1
T2
T3
T4
CPU
Total Execution Time
Register Operands Fetch
ALU Operation Execute
Result Write Back
T1
T2
T3
T4
clk
CPU
相关PDF资料
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1-583853-1 CONN CONTACT TWIN LEAF 20-24AWG
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