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| 型号： | A3987SLPTR-T |
| 厂商： | Allegro Microsystems Inc |
| 文件页数： | 10/13页 |
| 文件大小： | 0K |
| 描述： | IC DRIVER MICROSTEPPING 24-TSSOP |
| 产品培训模块： | A3987 DMOS Microstepping |
| 标准包装： | 1 |
| 应用： | 步进电机驱动器 |
| 输出数： | 1 |
| 电流 - 输出： | ±1.5A |
| 电压 - 负载： | 8 V ~ 50 V |
| 电源电压： | 3 V ~ 5.5 V |
| 工作温度： | -20°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-TSSOP（0.173"，4.40mm）裸露焊盘 |
| 供应商设备封装： | 24-TSSOP 裸露焊盘 |
| 包装： | 标准包装 |
| 产品目录页面： | 1141 (CN2011-ZH PDF) |
| 其它名称： | 620-1171-6 |
A3987
DMOS Microstepping Driver with Translator
the internal body diodes, and switching transients related to the
capacitance of the load. The blank time, t BLANK , is internally set
to approximately 1 μ s.
Charge Pump (CP1 and CP2) The charge pump is used to
generate a gate supply greater than V BB x to drive the source FET
gates. A 0.1 μ F ceramic capacitor is required between CP1 and
CP2 for pumping purposes. A 0.1 μ F ceramic capacitor is required
between VCP and the VBB terminals to act as a reservoir to oper-
ate the high-side FETs.
Internal Regulator (VREG) The VREG terminal should
be decoupled with a 0.22 μ F capacitor to ground. This internally
generated voltage is used to operate the sink FET outputs. VREG
is internally monitored, and in the case of a fault condition, the
outputs of the device are disabled.
Enable Input (ENABLE) This input activates all of the FET
outputs. When logic high, the outputs are disabled, and when
logic low, the outputs are enabled. Inputs to the translator (STEP,
DIR, MS1, and MS2) are always active, except in Sleep mode,
regardless of the ENABLE input state.
Shutdown In the event of a fault (either excessive junction
temperature, or low voltage on VCP), the outputs of the device
are disabled until the fault condition is removed. At power-up,
the undervoltage lockout (UVLO) circuit disables the drivers and
resets the translator to the home state.
Mixed Decay Operation The full bridges can operate in
mixed decay mode when set by the step sequence (see figures 3
through 5). As the trip point is reached, the device goes into fast
decay mode for 30.1% of the fixed off-time, t OFF . After this fast
Fault latched
2 A / div.
500 ns / div.
Figure 6. Short-to-ground event
decay portion, t FD , the device switches to slow decay mode for
the remainder of the fixed off-time period.
Synchronous Rectification When a PWM off-cycle is
triggered by an internal fixed off-time cycle, load current will
recirculate according to the decay mode selected by the control
logic. The A3987 synchronous rectification feature turns on the
appropriate FETs during current decay, effectively shorting out
the body diodes in the low R DS(on) driver. This lowers power
dissipation significantly, and can eliminate the need for external
Schottky diodes for many applications. To prevent reversal of
load current, synchronous rectification is turned off when a zero
current level is detected.
Short-to-Ground Should a motor winding short to ground,
the current through the short will rise until the overcurrent thresh-
old, I COPST , a minimum of 2 A, is exceeded. The driver turns off
after a short propagation delay and latches the fault. The device
will remain disabled until the SLEEP/RESET input goes high or
VDD power is removed. As shown in figure 6, a short-to-ground
produces a single overcurrent event.
Shorted Load During a shorted load event, the current path is
through the sense resistor. During this fault condition the device
will be protected, however, the fault will not be latched. When
the full bridge turns on, the current will rise and exceed the over-
current threshold. After the blank time,t BLANK , of approximatly
1 μ s, the driver will look at the voltage on the SENSE x pin. The
voltage on the SENSE x pin will be larger than the voltage set by
the REF pin, and the full bridge will turn off for the time set by
the ROSC pin. Figure 7 shows a shorted load condition with an
off-time of 30 μ s.
t off = 30 μ s
2 A / div.
5 μ s / div.
Figure 7. Short-to-load event
Allegro MicroSystems, LLC
115 Northeast Cutoff, Box 15036
10
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
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相关代理商/技术参数 |
参数描述 |
|---|---|
| A3987SLPTR-T | 制造商:Allegro MicroSystems 功能描述:IC MOTOR DRIVER DMOS 1.5A TSSOP-24 |
| A3988 | 制造商:ALLEGRO 制造商全称:Allegro MicroSystems 功能描述:Quad DMOS Full Bridge PWM Motor Driver |
| A3988_11 | 制造商:ALLEGRO 制造商全称:Allegro MicroSystems 功能描述:The A3988 is a quad DMOS full-bridge driver capable of driving up to two stepper motors or four DC motors. |
| A3988SEV-T | 制造商:Allegro MicroSystems 功能描述:DMOS Full Bridge PWM Motor Driver 36-Pin QFN EP Tube 制造商:Allegro MicroSystems 功能描述:Motor Driver IC |
| A3988SEVTR-1-T | 功能描述:MOTOR DRIVER 36QFN 制造商:allegro microsystems, llc 系列:- 零件状态:有效 标准包装:1,500 |
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