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参数资料
| 型号： | A14100A-1CQ256B |
| 元件分类： | FPGA |
| 英文描述： | FPGA, 1377 CLBS, 30000 GATES, 100 MHz, CQFP256 |
| 封装： | CERAMIC, CQFP-256 |
| 文件页数： | 54/54页 |
| 文件大小： | 333K |
| 代理商： | A14100A-1CQ256B |
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RadTolerant FPGAs
v3.1
1-5
output track is dedicated to the output of a particular
module. Long segments are uncommitted and can be
assigned during routing. Each output segment spans
four channels (two above and two below), except near
the top and bottom of the array where edge effects
occur. Long vertical tracks contain either one or two
segments. An example of vertical routing tracks and
segments is shown in Figure 1-5.
Antifuse Structures
An antifuse is a "normally open" structure as opposed to
the normally closed fuse structure used in PROMs
(programmable read-only memory) or PALs (programmed
array logic). The use of antifuses to implement a PLD
(programmable logic device) results in highly testable
structures, as well as efficient programming algorithms.
The structure is highly testable because there are no pre-
existing connections, enabling temporary connections to
be
made
using
pass
transistors.
These
temporary
connections can isolate individual antifuses to be
programmed, and also isolate individual circuit structures
to be tested. This can be done both before and after
programming. For example, all metal tracks can be tested
for continuity and shorts between adjacent tracks, and
the functionality of all logic modules can be verified.
Figure 1-5 Routing Structure
Vertical Routing Tracks
Segmented
Horizontal
Routing
Tracks
Logic
Modules
Antifuses
Table 1-1 Actel MIL-STD-883 Product Flow
Step
Screen
883 Method
883 - Class B
Requirement
1.
Internal Visual
2010, Test Condition B
100%
2.
Temperature Cycling
1010, Test Condition C
100%
3.
Constant Acceleration
2001, Test Condition D or E, Y1, Orientation Only
100%
4.
Seal
a. Fine
b. Gross
1014
100%
5.
Visual Inspection
2009
100%
6.
Pre-Burn-In Electrical Parameters
In accordance with applicable Actel device specification
100%
7.
Burn-in Test
1015, Condition D, 160 hours @ 125°C or 80 hours @ 150°C
100%
8.
Interim (Post-Burn-In) Electrical
Parameters
In accordance with applicable Actel device specification
100%
9.
Percent Defective Allowable
5%
All Lots
10.
Final Electrical Test
a. Static Tests
(1) 25°C (Subgroup 1, Table I)
(2) –55°C and +125°C
(Subgroups 2, 3, Table I)
b. Functional Tests
(1) 25°C (Subgroup 7, Table I)
(2) –55°C and +125°C
(Subgroups 8A and 8B, Table I)
c. Switching Tests at 25°C
(Subgroup 9, Table I)
In accordance with applicable Actel device specification, which
includes a, b, and c:
5005
100%
11.
External Visual
2009
100%
Note: When Destructive Physical Analysis (DPA) is performed on Class B devices, the step coverage requirement as specified in Method
2018 must be waived.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| A14100A-1CQ256BX3 | 制造商:Microsemi Corporation 功能描述:FPGA,ACT3 FAMILY,OTP DEVICE,5V SINGLE LOT DATE CODE - Trays |
| A14100A-1CQ256C | 功能描述:IC FPGA 10K GATES 256-CQFP RoHS:否 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:ACT™ 3 标准包装:1 系列:ProASICPLUS LAB/CLB数:- 逻辑元件/单元数:- RAM 位总计:129024 输入/输出数:248 门数:600000 电源电压:2.3 V ~ 2.7 V 安装类型:表面贴装 工作温度:- 封装/外壳:352-BFCQFP，带拉杆 供应商设备封装:352-CQFP（75x75） |
| A14100A-1CQ256E | 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:HiRel FPGAs |
| A14100A-1CQ256M | 制造商:Microsemi Corporation 功能描述:FPGA ACT 3 Family 10K Gates 1377 Cells 125MHz 0.8um Technology 5V 256-Pin CQFP 制造商:Microsemi Corporation 功能描述:FPGA ACT 3 10K GATES 1377 CELLS 125MHZ 0.8UM 5V 256CQFP - Trays 制造商:Microsemi Corporation 功能描述:IC FPGA 10K GATES 256-CQFP MIL |
| A14100A-1PG256B | 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:HiRel FPGAs |
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