- 您现在的位置：买卖IC网 > PDF目录294782 > A1020B-CQ84C FPGA, 547 CLBS, 2000 GATES, 37 MHz, CQFP84 PDF资料下载
参数资料
| 型号： | A1020B-CQ84C |
| 元件分类： | FPGA |
| 英文描述： | FPGA, 547 CLBS, 2000 GATES, 37 MHz, CQFP84 |
| 封装： | CERAMIC, CQFP-84 |
| 文件页数： | 29/54页 |
| 文件大小： | 333K |
| 代理商： | A1020B-CQ84C |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页当前第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页
RadTolerant FPGAs
v3.1
1-31
Pin Descriptions
CLK
Clock (Input)
RT1020 and A1020B only. TTL clock input for global clock
distribution networks. The clock input is buffered prior
to clocking the logic modules. This pin can also be used
as an I/O.
CLKA
Clock A (Input)
Not applicable for RT1020 and A1020B. TTL clock input
for global clock distribution networks. The clock input is
buffered prior to clocking the logic modules. This pin can
also be used as an I/O.
CLKB
Clock B (Input)
Not applicable for RT1020 and A1020B. TTL clock input
for global clock distribution networks. The clock input is
buffered prior to clocking the logic modules. This pin can
also be used as an I/O.
DCLK
Diagnostic Clock (Input)
TTL clock input for diagnostic probe and device
programming. DCLK is active when the MODE pin is
HIGH. This pin functions as an I/O when the MODE pin is
LOW.
GND
Ground
LOW supply voltage.
HCLK
Dedicated (Hard-Wired) Array Clock
(Input)
Not applicable for RT1020, A1020B, RT1280A and
A1280A. TTL clock input for sequential modules. This
input is directly wired to each S-module, offering clock
speeds independent of the number of S-modules being
driven. This pin can also be used as an I/O.
I/O
Input/Output (Input, Output)
I/O pin functions as an input, output, tristate, or
bidirectional buffer.
Input
and
output
levels
are
compatible with standard TTL and CMOS specifications.
In the RT1020, A1020B, RT1280, and A1280A devices,
unused I/O pins are automatically driven LOW. In the
RT1425,
A1425A,
RT1460,
A1460A,
RT14100,
and
A14100A devices, unused I/O pins are automatically
tristated.
IOCLK
Dedicated (Hard-Wired) I/O Clock (Input)
Not applicable for RT1020, A1020B, RT1280A and
A1280A. TTL clock input for I/O modules. This input is
directly wired to each I/O module, offering clock speeds
independent of the number of I/O modules being driven.
This pin can also be used as an I/O.
IOPCL
Dedicated (Hard-Wired) I/O
Preset/Clear (Input)
Not applicable for RT1020, A1020B, RT1280A and
A1280A. TTL input for I/O preset or clear. This global
input is directly wired to the preset and clear inputs of all
I/O registers. This pin functions as an I/O when no I/O
preset or clear macros are used.
MODE
Mode (Input)
The MODE pin controls the use of diagnostic pins (DCLK,
PRA, PRB, SDI). When the MODE pin is HIGH, the special
functions are active. When the MODE pin is LOW, the
pins function as I/Os. To provide debugging capability,
the MODE pin should be terminated to GND through a
10 k
Ω resistor so that the MODE pin can be pulled HIGH
when required.
NC
No Connection
This pin is not connected to circuitry within the device.
PRA, I/O
Probe A (Output)
The Probe A pin is used to output data from any user-
defined design node within the device. This independent
diagnostic pin can be used in conjunction with the Probe
B pin to allow real-time diagnostic output of any signal
path within the device. The Probe A pin can be used as a
user-defined I/O when verification has been completed.
The pin’s probe capabilities can be permanently disabled
to protect programmed design confidentiality. PRA is
accessible when the MODE pin is HIGH. This pin functions
as an I/O when the MODE pin is LOW.
PRB, I/O
Probe B (Output)
The Probe B pin is used to output data from any user-
defined design node within the device. This independent
diagnostic pin can be used in conjunction with the Probe
A pin to allow real-time diagnostic output of any signal
path within the device. The Probe B pin can be used as a
user-defined I/O when verification has been completed.
The pin’s probe capabilities can be permanently disabled
to protect programmed design confidentiality. PRB is
accessible when the MODE pin is HIGH. This pin functions
as an I/O when the MODE pin is LOW.
SDI
Serial Data Input (Input)
Serial data input for diagnostic probe and device
programming. SDI is active when the MODE pin is HIGH.
This pin functions as an I/O when the MODE pin is LOW.
VCC
5.0 V Supply Voltage
HIGH supply voltage.
相关PDF资料 |
PDF描述 |
|---|---|
| A14100A-1CQ256B | FPGA, 1377 CLBS, 30000 GATES, 100 MHz, CQFP256 |
| A1280A-1CQ172E | FPGA, 1232 CLBS, 8000 GATES, 60 MHz, CQFP172 |
| A1460A-1CQ196E | FPGA, 848 CLBS, 6000 GATES, 100 MHz, CQFP196 |
| A1460A-1PG207E | FPGA, 848 CLBS, 6000 GATES, 100 MHz, CPGA207 |
| A1460A-CQ196E | FPGA, 848 CLBS, 6000 GATES, 85 MHz, CQFP196 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| A1020B-CQ84E | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Field Programmable Gate Array (FPGA) |
| A1020B-CQ84M | 制造商:Microsemi Corporation 功能描述:IC FPGA 2K GATES 84-CQFP MIL 制造商:Microsemi Corporation 功能描述:IC FPGA 69 I/O 84CQFP |
| A1020B-PG84B | 制造商:Microsemi SOC Products Group 功能描述:FPGA ACT 1 2K GATES 547 CELLS 48MHZ 1.0UM 5V 84CPGA - Trays 制造商:Microsemi Corporation 功能描述:IC FPGA 2K GATES 84-CPGA MIL |
| A1020B-PG84C | 功能描述:IC FPGA 2K GATES 84-CPGA COM RoHS:否 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:ACT™ 1 标准包装:1 系列:ProASICPLUS LAB/CLB数:- 逻辑元件/单元数:- RAM 位总计:129024 输入/输出数:248 门数:600000 电源电压:2.3 V ~ 2.7 V 安装类型:表面贴装 工作温度:- 封装/外壳:352-BFCQFP，带拉杆 供应商设备封装:352-CQFP（75x75） |
| A1020B-PG84E | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Field Programmable Gate Array (FPGA) |
发布紧急采购，3分钟左右您将得到回复。