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参数资料
| 型号： | A1020B-CQ84C |
| 元件分类： | FPGA |
| 英文描述： | FPGA, 547 CLBS, 2000 GATES, 37 MHz, CQFP84 |
| 封装： | CERAMIC, CQFP-84 |
| 文件页数： | 2/54页 |
| 文件大小： | 333K |
| 代理商： | A1020B-CQ84C |
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RadTolerant FPGAs
1- 6
v3.1
Table 1-2 Actel Extended Flow1
Step
Screen
Method
Requirement
1.
Wafer Lot Acceptance2
5007 with Step Coverage Waiver
All Lots
2.
Destructive In-Line Bond Pull3
2011, Condition D
Sample
3.
Internal Visual
2010, Condition A
100%
4.
Serialization
100%
5.
Temperature Cycling
1010, Condition C
100%
6.
Constant Acceleration
2001, Condition D or E, Y1 Orientation Only
100%
7.
Particle Impact Noise Detection
2020, Condition A
100%
8.
Radiographic
2012
100%
9.
Pre-Burn-In Test
In accordance with applicable Actel device specification
100%
10.
Burn-in Test
1015, Condition D, 240 hours @ 125°C minimum
100%
11.
Interim (Post-Burn-In) Electrical Parameters
In accordance with applicable Actel device specification
100%
12.
Reverse Bias Burn-In
1015, Condition C, 72 hours @ 150°C minimum
100%
13.
Interim (Post-Burn-In) Electrical Parameters
In accordance with applicable Actel device specification
100%
14.
Percent Defective Allowable (PDA)
Calculation
5%, 3% Functional Parameters @ 25°C
All Lots
15.
Final Electrical Test
a. Static Tests
(1) 25°C (Subgroup 1, Table1)
(2) –55°C and +125°C
(Subgroups 2, 3, Table 1)
b. Functional Tests
(1) 25°C (Subgroup 7, Table 15)
(2) –55°C and +125°C
(Subgroups 8A and B, Table 1)
c. Switching Tests at 25°C
(Subgroup 9, Table 1)
In accordance with Actel applicable device specification,
which includes a, b, and c:
5005
100%
16.
Seal
a. Fine
b. Gross
1014
100%
17.
External Visual
2009
100%
Notes:
1. Actel offers the extended flow for customers that require additional screening beyond the requirements of MIL-STD-883, Class B.
Actel is compliant to the requirements of MIL-STD-883, Paragraph 1.2.1, and MIL-I-38535, Appendix A. Actel is offering this
extended flow incorporating the majority of the screening procedures as outlined in Method 5004 of MIL-STD-883 Class S. The
exceptions to Method 5004 are shown in notes 2 and 3 below.
2. Wafer lot acceptance is performed to Method 5007; however, the step coverage requirement as specified in Method 2018 must be
waived.
3. Method 5004 requires a 100 percent, non-destructive bond pull (Method 2023). Actel substitutes a destructive bond pull (Method
2011), Condition D on a sample basis only.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| A1020B-CQ84E | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Field Programmable Gate Array (FPGA) |
| A1020B-CQ84M | 制造商:Microsemi Corporation 功能描述:IC FPGA 2K GATES 84-CQFP MIL 制造商:Microsemi Corporation 功能描述:IC FPGA 69 I/O 84CQFP |
| A1020B-PG84B | 制造商:Microsemi SOC Products Group 功能描述:FPGA ACT 1 2K GATES 547 CELLS 48MHZ 1.0UM 5V 84CPGA - Trays 制造商:Microsemi Corporation 功能描述:IC FPGA 2K GATES 84-CPGA MIL |
| A1020B-PG84C | 功能描述:IC FPGA 2K GATES 84-CPGA COM RoHS:否 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:ACT™ 1 标准包装:1 系列:ProASICPLUS LAB/CLB数:- 逻辑元件/单元数:- RAM 位总计:129024 输入/输出数:248 门数:600000 电源电压:2.3 V ~ 2.7 V 安装类型:表面贴装 工作温度:- 封装/外壳:352-BFCQFP，带拉杆 供应商设备封装:352-CQFP（75x75） |
| A1020B-PG84E | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Field Programmable Gate Array (FPGA) |
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