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参数资料
型号： 951413CGLF
厂商： INTEGRATED DEVICE TECHNOLOGY INC
元件分类： 时钟产生/分配
英文描述： 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56
封装： 6.10 MM, 0.50 MM PITCH, GREEN, MO-153, TSSOP-56
文件页数： 7/26页
文件大小： 257K
代理商： 951413CGLF
15
Integrated
Circuit
Systems, Inc.
ICS951413
0929D—10/30/06
Absolute Max
Symbol
Parameter
Min
Max
Units
VDD_A
3.3V Core Supply Voltage
VDD + 0.5V
V
VDD_In
3.3V Logic Input Supply Voltage
GND - 0.5
VDD + 0.5V
V
Ts
Storage Temperature
-65
150
°C
Tambient
Ambient Operating Temp
0
70
°C
Tcase
Case Temperature
115
°C
ESD prot
Input ESD protection
human body model
2000
V
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS Notes
Input High Voltage
VIH
3.3 V +/-5%
2
VDD + 0.3
V
1
Input Low Voltage
VIL
3.3 V +/-5%
VSS - 0.3
0.8
V
1
Input High Current
IIH
VIN = VDD
-5
5
uA
1
IIL1
VIN = 0 V; Inputs with no pull-
up resistors
-5
uA
1
IIL2
VIN = 0 V; Inputs with pull-up
resistors
-200
uA
1
Low Threshold Input-
High Voltage
VIH_FS
3.3 V +/-5%
0.7
VDD + 0.3
V
1
Low Threshold Input-
Low Voltage
VIL_FS
3.3 V +/-5%
VSS - 0.3
0.35
V
1
Operating Current
IDD3.3OP
all outputs driven
400
mA
1
all diff pairs driven
70
mA
1
all differential pairs tri-stated
12
mA
1
Input Frequency
Fi
VDD = 3.3 V
14.31818
MHz
3
Pin Inductance
Lpin
7nH
1
CIN
Logic Inputs
5
pF
1
COUT
Output pin capacitance
6
pF
1
CINX
X1 & X2 pins
5
pF
1
Clk Stabilization
TSTAB
From VDD Power-Up or de-
assertion of PD# to 1st clock
1.8
ms
1,2
Modulation Frequency
Triangular Modulation
30
33
kHz
1
Tdrive_PD#
CPU output enable after
PD# de-assertion
300
us
1
Tfall_Pd#
PD# fall time of
5
ns
1
Trise_Pd#
PD# rise time of
5
ns
2
SMBus Voltage
VDD
2.7
5.5
V
1
Low-level Output Voltage
VOL
@ IPULLUP
0.4
V
1
Current sinking at
VOL = 0.4 V
IPULLUP
4mA
1
SCLK/SDATA
Clock/Data Rise Time
TRI2C
(Max VIL - 0.15) to
(Min VIH + 0.15)
1000
ns
1
SCLK/SDATA
Clock/Data Fall Time
TFI2C
(Min VIH + 0.15) to
(Max VIL - 0.15)
300
ns
1
1Guaranteed by design and characterization, not 100% tested in production.
2See timing diagrams for timing requirements.
ppm frequency accuracy on PLL outputs.
3 Input frequency should be measured at the REFOUT pin and tuned to ideal 14.31818MHz to meet
Input Low Current
Powerdown Current
IDD3.3PD
Input Capacitance
相关PDF资料
PDF描述
951413CFLFT 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56
951413CFLF 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56
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951416AFLF 220 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56
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相关代理商/技术参数
参数描述
951413CGLFT 制造商:Integrated Device Technology Inc 功能描述:Programmable PLL Clock Generator Triple 56-Pin TSSOP T/R
951414-2011309-AR-PT 功能描述:集管和线壳 14P BD STCK HDR 2R STRT SMT 10U AU RoHS:否 产品种类:1.0MM Rectangular Connectors 产品类型:Headers - Pin Strip 系列:DF50 触点类型:Pin (Male) 节距:1 mm 位置/触点数量:16 排数:1 安装风格:SMD/SMT 安装角:Right 端接类型:Solder 外壳材料:Liquid Crystal Polymer (LCP) 触点材料:Brass 触点电镀:Gold 制造商:Hirose Connector
951414-2011309-AR-TP 功能描述:集管和线壳 14P BD STCK HDR 2R STRT SMT 10U AU RoHS:否 产品种类:1.0MM Rectangular Connectors 产品类型:Headers - Pin Strip 系列:DF50 触点类型:Pin (Male) 节距:1 mm 位置/触点数量:16 排数:1 安装风格:SMD/SMT 安装角:Right 端接类型:Solder 外壳材料:Liquid Crystal Polymer (LCP) 触点材料:Brass 触点电镀:Gold 制造商:Hirose Connector
951414-2011409-AR-PT 功能描述:集管和线壳 14P BD STCK HDR 2R STRT SMT 10U AU RoHS:否 产品种类:1.0MM Rectangular Connectors 产品类型:Headers - Pin Strip 系列:DF50 触点类型:Pin (Male) 节距:1 mm 位置/触点数量:16 排数:1 安装风格:SMD/SMT 安装角:Right 端接类型:Solder 外壳材料:Liquid Crystal Polymer (LCP) 触点材料:Brass 触点电镀:Gold 制造商:Hirose Connector
951414-2011409-AR-TP 功能描述:集管和线壳 14P BD STCK HDR 2R STRT SMT 10U AU RoHS:否 产品种类:1.0MM Rectangular Connectors 产品类型:Headers - Pin Strip 系列:DF50 触点类型:Pin (Male) 节距:1 mm 位置/触点数量:16 排数:1 安装风格:SMD/SMT 安装角:Right 端接类型:Solder 外壳材料:Liquid Crystal Polymer (LCP) 触点材料:Brass 触点电镀:Gold 制造商:Hirose Connector
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