参数资料
型号: 951413CGLF
厂商: INTEGRATED DEVICE TECHNOLOGY INC
元件分类: 时钟产生/分配
英文描述: 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56
封装: 6.10 MM, 0.50 MM PITCH, GREEN, MO-153, TSSOP-56
文件页数: 12/26页
文件大小: 257K
代理商: 951413CGLF
2
Integrated
Circuit
Systems, Inc.
ICS951413
0929D—10/30/06
Pin Description
PIN #
PIN NAME
PIN
TYPE
DESCRIPTION
1X1
IN
Crystal input, Nominally 14.318MHz.
2X2
OUT Crystal output, Nominally 14.318MHz
3
VDD48
PWR Power pin for the 48MHz output.3.3V
4
USB_48MHz
OUT 48.00MHz USB clock
5
GND
PWR Ground pin.
6
VTT_PWRGD#/PD
IN
Vtt_PwrGd# is an active low input used to determine when latched inputs are
ready to be sampled. PD is an asynchronous active high input pin used to put
the device into a low power state. The internal clocks, PLLs and the crystal
oscillator are stopped.
7
SCLK
IN
Clock pin of SMBus circuitry, 5V tolerant.
8
SDATA
I/O
Data pin for SMBus circuitry, 5V tolerant.
9
**FS_C
IN
Frequency select latch input pin
10
**CLKREQA#
IN
Output enable for PCI Express (SRC) outputs. SMBus selects which outputs
are controlled.
0 = enabled, 1 = tri-stated
11
**CLKREQB#
IN
Output enable for PCI Express (SRC) outputs. SMBus selects which outputs
are controlled.
0 = enabled, 1 = tri-stated
12
SRCCLKT7
OUT True clock of differential SRC clock pair.
13
SRCCLKC7
OUT Complement clock of differential SRC clock pair.
14
VDDSRC
PWR Supply for SRC clocks, 3.3V nominal
15
GNDSRC
PWR Ground pin for the SRC outputs
16
SRCCLKT6
OUT True clock of differential SRC clock pair.
17
SRCCLKC6
OUT Complement clock of differential SRC clock pair.
18
SRCCLKT5
OUT True clock of differential SRC clock pair.
19
SRCCLKC5
OUT Complement clock of differential SRC clock pair.
20
GNDSRC
PWR Ground pin for the SRC outputs
21
VDDSRC
PWR Supply for SRC clocks, 3.3V nominal
22
SRCCLKT4
OUT True clock of differential SRC clock pair.
23
SRCCLKC4
OUT Complement clock of differential SRC clock pair.
24
SRCCLKT3
OUT True clock of differential SRC clock pair.
25
SRCCLKC3
OUT Complement clock of differential SRC clock pair.
26
GNDSRC
PWR Ground pin for the SRC outputs
27
ATIGCLKT1
OUT True clock of differential ATIGCLK clock pair.
28
ATIGCLKC1
OUT Complementary clock of differential ATIGCLK clock pair.
相关PDF资料
PDF描述
951413CFLFT 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56
951413CFLF 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56
951416AGLF 220 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56
951416AFLF 220 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56
951416AGLFT 220 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56
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