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参数资料
| 型号： | 950218AFLFT |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 200.4 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封装： | 0.300 INCH, SSOP-48 |
| 文件页数： | 1/20页 |
| 文件大小： | 331K |
| 代理商： | 950218AFLFT |
Integrated
Circuit
Systems, Inc.
ICS950218
Preliminary Product Preview
*MULTISEL1/REF1
VDDREF
X1
X2
GND
*FS2/PCICLK0
*FS3/PCICLK1
SEL48_24#/PCICLK2
VDDPCI
*FS4/PCICLK3
PCICLK4
PCICLK5
GND
PCICLK6
PCICLK7
PCICLK8
PCICLK9
VDDPCI
Vtt_PWRGD#
RESET#
GND
*FS0/48MHz
*FS1/24_48MHz
AVDD48
1
**
REF0/MULTSEL0*
GND
VDDCPU
CPUCLKT2
CPUCLKC2
GND
PD#
CPUCLKT0
CPUCLKC0
VDDCPU
CPUCLKT1
CPUCLKC1
GND
I REF
AVDD
GND
VDD3V66
3V66_0
3V66_1
GND
3V66_2
3V66_48MHz/SEL66_48#
SCLK
SDATA
*
ICS950218
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
Block Diagram
950218 Rev A 01/23/02
Pin Configuration
Recommended Application:
CK-408 clock with driven mode only for Brookdale
and Brookdale-G chipset with P4 processor.
Output Features:
3 - Pairs of differential CPU clocks (differential current
mode)
3 - 3V66 @ 3.3V
10 - PCI @ 3.3V
1 - 48MHz @ 3.3V fixed
2 - REF @ 3.3V, 14.318MHz
1 - 48_66MHz selectable @ 3.3V fixed
1 - 24_48MHz selectable @ 3.3V
Features/Benefits:
Programmable output frequency.
Programmable output divider ratios.
Programmable output rise/fall time.
Programmable output skew.
Programmable spread percentage for EMI control.
Watchdog timer technology to reset system
if system malfunctions.
Programmable watch dog safe frequency.
Support I
2C Index read/write and block read/write
operations.
Uses external 14.318MHz crystal.
Key Specifications:
CPU Output Jitter <150ps
3V66 Output Jitter <250ps
CPU Output Skew <100ps
Programmable Timing Control Hub for P4
48-Pin 300-mil SSOP
PLL2
PLL1
Spread
Spectrum
48MHz
PCICLK (9:0)
3V66 (2:0)
24_48MHz
X1
X2
XTAL
OSC
CPU
DIVDER
PCI
DIVDER
3V66
DIVDER
PD#
MULTSEL(1:0)
SDATA
SCLK
Vtt_PWRGD#
SEL 48_24#
SEL 66_48#
FS (4:0)
I REF
RESET#
Control
Logic
Config.
Reg.
REF (1:0)
3
10
4
3
CPUCLKT (2:0)
CPUCLKC (2:0)
/ 2
3V66
DIVDER
3V66_48MHz
2
ti
B7
ti
B6
ti
B5
ti
B4
ti
B
K
L
C
U
P
C
z
H
M
6
V
3
z
H
M
K
L
C
I
C
P
z
H
M
4
S
F3
S
F2
S
F1
S
F0
S
F
00
0
.
2
0
10
0
.
8
60
0
.
4
3
00
0
1
0
.
5
0
10
0
.
0
70
0
.
5
3
00
0
1
0
.
8
0
10
0
.
2
70
0
.
6
3
00
0
1
0
.
1
10
0
.
4
70
0
.
7
3
00
1
0
.
4
1
10
0
.
6
70
0
.
8
3
00
1
0
1
0
.
7
1
10
0
.
8
70
0
.
9
3
00
1
0
.
0
2
10
0
.
0
80
0
.
0
4
00
1
0
.
3
2
10
0
.
2
80
0
.
1
4
01
0
.
6
2
10
0
.
2
70
0
.
6
3
01
0
1
0
.
0
3
10
3
.
4
70
1
.
7
3
01
0
1
0
.
6
3
10
0
.
8
60
0
.
4
3
01
0
1
0
.
0
4
10
0
.
0
70
0
.
5
3
01
1
0
.
4
10
0
.
2
70
0
.
6
3
01
1
0
1
0
.
8
4
10
0
.
4
70
0
.
7
3
01
1
0
.
2
5
10
0
.
6
70
0
.
8
3
01
1
0
.
6
5
10
0
.
8
70
0
.
9
3
10
0
.
0
6
10
0
.
0
80
0
.
0
4
10
0
1
0
.
4
6
10
0
.
2
80
0
.
1
4
10
0
1
0
6
.
6
10
6
.
6
60
3
.
3
10
0
1
0
.
0
7
10
0
.
8
60
0
.
4
3
10
1
0
.
5
7
10
0
.
0
70
0
.
5
3
10
1
0
1
0
.
0
8
10
0
.
2
70
0
.
6
3
10
1
0
.
5
8
10
0
.
4
70
0
.
7
3
10
1
0
.
0
9
10
0
.
6
70
0
.
8
3
11
0
8
.
6
60
8
.
6
60
4
.
3
11
0
1
0
2
.
0
10
8
.
6
60
4
.
3
11
0
1
0
6
.
3
10
8
.
6
60
4
.
3
11
0
1
0
4
.
0
20
8
.
6
60
4
.
3
11
1
0
6
.
6
60
6
.
6
60
3
.
3
11
1
0
1
0
.
0
10
6
.
6
60
3
.
3
11
1
0
.
0
20
6
.
6
60
3
.
3
11
1
3
.
3
10
6
.
6
60
3
.
3
Frequency Table
1 This output has 2X drive
* Internal Pull-up resistor of 120K to VDD
** Internal Pull-down resistor of 120K to GND
PRODUCT PREVIEW documents contain information on new products in the sampling or preproduction phase of development. Characteristic data and
other specifications are subject to change without notice.
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| 950220AFLFT | 功能描述:时钟发生器及支持产品 RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
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