参数资料
| 型号： | 71M6521FE-DB |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 44/107页 |
| 文件大小： | 0K |
| 描述： | BOARD DEMO FOR 71M6521FE |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 1 |
| 主要目的： | 电源管理，电度表/功率表 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | 71M6521 |
| 已供物品： | 2 个板，线缆，CD，电源 |
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71M6521DE/DH/FE Data Sheet
Three-Wire EEPROM Interface
A 500kHz three-wire interface, using SDATA, SCK, and a DIO pin for CS is available. The interface is selected with
DIO_EEX =3. The same 2-wire EECTRL register is used, except the bits are reconfigured, as shown in Table 58. When
EECTRL is written, up to 8 bits from EEDATA are either written to the EEPROM or read from the EEPROM, depending
on the values of the EECTRL bits.
Control
Bit
7
6
5
4
3-0
Name
WFR
BUSY
HiZ
RD
CNT [3:0]
Read/Write
W
R
W
W
W
Description
Wait for Ready. If this bit is set, the trailing edge of BUSY will be delayed
until a rising edge is seen on the data line. This bit can be used during
the last byte of a Write command to cause the INT5 interrupt to occur
when the EEPROM has finished its internal write sequence. This bit is
ignored if HiZ=0.
Asserted while serial data bus is busy. When the BUSY bit falls, an INT5
interrupt occurs.
Indicates that the SD signal is to made high impedance immediately after
the last SCK rising edge.
Indicates that EEDATA is to be filled with data from EEPROM.
Specifies the number of clocks to be issued. Allowed values are 0
through 8. If RD=1, CNT bits of data will be read MSB first, and right
justified into the low order bits of EEDATA . If RD=0, CNT bits will be sent
MSB first to EEPROM, shifted out of EEDATA’s MSB. If CNT is zero,
SDATA will simply obey the HiZ bit.
Table 58: EECTRL bits for 3-wire interface
The timing diagrams in Figure 9 through Figure 13 describe the 3-wire EEPROM interface behavior. All commands
begin when the EECTRL register is written. Transactions start by first raising the DIO pin that is connected to CS.
Multiple 8-bit or less commands such as those shown in Figure 9 through Figure 13 are then sent via EECTRL and
EEDATA . When the transaction is finished, CS must be lowered. At the end of a Read transaction, the EEPROM will
be driving SDATA, but will transition to HiZ (high impedance) when CS falls. The firmware should then immediately
issue a write command with CNT=0 and HiZ=0 to take control of SDATA and force it to a low-Z state.
EECTRL Byte Written
Write -- No HiZ
SCLK (output)
CNT Cycles (6 shown)
INT5
SDATA (output)
D7
D6
D5
D4
D3
D2
SDATA output Z
(LoZ)
BUSY (bit)
Figure 9: 3-Wire Interface. Write Command, HiZ=0.
EECTRL Byte Written
Write -- With HiZ
SCLK (output)
CNT Cycles (6 shown)
INT5
SDATA (output)
D7
D6
D5
D4
D3
D2
SDATA output Z
(LoZ)
(HiZ)
BUSY (bit)
Figure 10: 3-Wire Interface. Write Command, HiZ=1
Page: 44 of 107
Rev 3
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相关代理商/技术参数 |
参数描述 |
|---|---|
| 71M6521FE-IGT | 制造商:Maxim Integrated Products 功能描述:Metering Systems on a Chip - SoC Residential Energy Meter IC |
| 71M6521FE-IGT/F | 功能描述:计量片上系统 - SoC Residential Energy Meter IC RoHS:否 制造商:Maxim Integrated 核心:80515 MPU 处理器系列:71M6511 类型:Metering SoC 最大时钟频率:70 Hz 程序存储器大小:64 KB 数据 RAM 大小:7 KB 接口类型:UART 可编程输入/输出端数量:12 片上 ADC: 安装风格:SMD/SMT 封装 / 箱体:LQFP-64 封装:Reel |
| 71M6521FE-IGT/F1 | 功能描述:计量片上系统 - SoC RoHS:否 制造商:Maxim Integrated 核心:80515 MPU 处理器系列:71M6511 类型:Metering SoC 最大时钟频率:70 Hz 程序存储器大小:64 KB 数据 RAM 大小:7 KB 接口类型:UART 可编程输入/输出端数量:12 片上 ADC: 安装风格:SMD/SMT 封装 / 箱体:LQFP-64 封装:Reel |
| 71M6521FE-IGTR | 制造商:Maxim Integrated Products 功能描述:Metering Systems on a Chip - SoC Residential Energy Meter IC |
| 71M6521FE-IGTR/F | 功能描述:计量片上系统 - SoC Residential Energy Meter IC RoHS:否 制造商:Maxim Integrated 核心:80515 MPU 处理器系列:71M6511 类型:Metering SoC 最大时钟频率:70 Hz 程序存储器大小:64 KB 数据 RAM 大小:7 KB 接口类型:UART 可编程输入/输出端数量:12 片上 ADC: 安装风格:SMD/SMT 封装 / 箱体:LQFP-64 封装:Reel |
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