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参数资料
| 型号： | 70V18L15PF8 |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | SRAM |
| 英文描述： | 64K X 9 DUAL-PORT SRAM, 15 ns, PQFP100 |
| 封装： | TQFP-100 |
| 文件页数： | 3/17页 |
| 文件大小： | 157K |
| 代理商： | 70V18L15PF8 |
11
IDT70V18L
High-Speed 3.3V 64K x 9 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
4854 drw 11
tDW
tAPS
ADDR"A"
tWC
DATAOUT "B"
MATCH
tWP
R/
W"A"
DATAIN "A"
ADDR"B"
tDH
VALID
(1)
MATCH
BUSY"B"
tBDA
VALID
tBDD
tDDD
(3)
tWDD
tBAA
Timing Waveform of Write with Port-to-Port Read and BUSY (M/S = VIH)(2,4,5)
Timing Waveform of Write with BUSY (M/S = VIL)
NOTES:
1. tWH must be met for both
BUSY input (SLAVE) and output (MASTER).
2.
BUSY is asserted on port "B" blocking R/W"B", until BUSY"B" goes HIGH.
3. tWB is only for the 'slave' version.
NOTES:
1. To ensure that the earlier of the two ports wins. tAPS is ignored for M/
S = VIL (SLAVE).
2.
CEL = CER = VIL, refer to Chip Enable Truth Table.
3.
OE = VIL for the reading port.
4. If M/
S = VIL (slave), BUSY is an input. Then for this example BUSY"A" = VIH and BUSY"B" input is shown above.
5. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from port "A".
4854 drw 12
R/
W"A"
BUSY"B"
tWB
(3)
R/
W"B"
tWH
(1)
(2)
tWP
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