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参数资料
| 型号： | 70V18L15PF8 |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | SRAM |
| 英文描述： | 64K X 9 DUAL-PORT SRAM, 15 ns, PQFP100 |
| 封装： | TQFP-100 |
| 文件页数： | 14/17页 |
| 文件大小： | 157K |
| 代理商： | 70V18L15PF8 |
IDT70V18L
High-Speed 3.3V 64K x 9 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
6
Timing of Power-Up Power-Down
Waveform of Read Cycles(5)
NOTES:
1. Timing depends on which signal is asserted last,
OE or CE.
2. Timing depends on which signal is de-asserted first
CE or OE.
3. tBDD delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations
BUSY has no
relation to valid output data.
4. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA or tBDD.
5.
SEM = VIH.
6. Refer toTruth Table I - Chip Enable.
CE(6)
4854 drw 06
tPU
ICC
ISB
tPD
50%
.
tRC
R/
W
CE(6)
ADDR
tAA
OE
4854 drw 05
(4)
tACE
(4)
tAOE
(4)
(1)
tLZ
tOH
(2)
tHZ
(3,4)
tBDD
DATAOUT
BUSYOUT
VALID DATA
(4)
AC Test Conditions
Figure 1. AC Output Load
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
GND to 3.0V
3ns Max.
1.5V
Figures 1 and 2
4854 tbl 11
4854 drw 04
590
30pF
435
3.3V
DATAOUT
BUSY
INT
590
5pF*
435
3.3V
DATAOUT
4854 drw 03
Figure 2. Output Test Load
(for tLZ, tHZ, tWZ, tOW)
* Including scope and jig.
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