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参数资料
| 型号： | 49LF002 |
| 厂商： | Silicon Storage Technology, Inc. |
| 英文描述： | 2 Mbit / 3 Mbit / 4 Mbit / 8 Mbit Firmware Hub |
| 中文描述： | 2兆位/ 3兆/ 4兆位/ 8兆固件集线器 |
| 文件页数： | 9/36页 |
| 文件大小： | 412K |
| 代理商： | 49LF002 |
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Advance Information
2 Mbit / 3 Mbit / 4 Mbit / 8 Mbit Firmware Hub
SST49LF002A / SST49LF003A / SST49LF004A / SST49LF008A
17
2001 Silicon Storage Technology, Inc.
S71161-06-000
9/01
504
TABLE
8: PIN DESCRIPTION
Symbol
Pin Name
Type1
Interface
Functions
PP
FWH
A10-A0
Address
I
X
Inputs for low-order addresses during Read and Write operations.
Addresses are internally latched during a Write cycle. For the pro-
gramming interface, these addresses are latched by R/C# and share
the same pins as the high-order address inputs.
DQ7-DQ0
Data
I/O
X
To output data during Read cycles and receive input data during
Write cycles. Data is internally latched during a Write cycle. The out-
puts are in tri-state when OE# is high.
OE#
Output Enable
I
X
To gate the data output buffers
WE#
Write Enable
I
X
To control the Write operations
IC
Interface
Configuration Pin
I
X
This pin determines which interface is operational. When held high,
programmer mode is enabled and when held low, FWH mode is
enabled. This pin must be setup at power-up or before return from
reset and not change during device operation. This pin is internally
pulled- down with a resistor between 20-100 K
.
INIT#
Initialize
I
X
This is the second reset pin for in-system use. This pin is internally
combined with the RST# pin; If this pin or RST# pin is driven low,
identical operation is exhibited.
ID[3:0]
Identification Inputs
I
X
These four pins are part of the mechanism that allows multiple parts
to be attached to the same bus. The strapping of these pins is used
to identify the component.The boot device must have ID[3:0]=0000
and it is recommended that all subsequent devices should use
sequential up-count strapping. These pins are internally pulled-down
with a resistor between 20-100 K
.
FGPI[4:0]
General Purpose Inputs
I
X
These individual inputs can be used for additional board flexibility.
The state of these pins can be read through GPI_REG register.
These inputs should be at their desired state before the start of the
PCI clock cycle during which the read is attempted, and should
remain in place until the end of the Read cycle. Unused GPI pins
must not be floated.
TBL#
Top Block Lock
I
X
When low, prevents programming to the Boot Block sectors at top of
memory. When TBL# is high it disables hardware write protection for
the top block sectors. This pin cannot be left unconnected.
FWH[3:0]
FWH I/Os
I/O
X
I/O Communications
CLK
Clock
I
X
To provide a clock input to the control unit
FWH4
FWH Input
I
X
Input Communications
RST#
Reset
I
X
To reset the operation of the device
WP#
Write Protect
I
X
When low, prevents programming to all but the highest addressable
blocks. When WP# is high it disables hardware write protection for
these blocks. This pin cannot be left unconnected.
R/C#
Row/Column Select
I
X
Select For the Programming interface, this pin determines whether
the address pins are pointing to the row addresses, or to the column
addresses.
RES
Reserved
X
These pins must be left unconnected.
VDD
Power Supply
I
X
To provide power supply (3.0-3.6V)
VSS
Ground
I
X
Circuit ground (OV reference) Every VSS pin must be grounded.
NC
No Connection
I
X
Unconnected pins
T8.3 504
1. I = Input, O = Output
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