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参数资料
| 型号： | 48e30 |
| 厂商： | Holtek Semiconductor Inc. |
| 英文描述： | 8-Bit I/O Type MCU (With EEPROM) |
| 中文描述： | 8位I / O型微控制器（带EEPROM） |
| 文件页数： | 11/44页 |
| 文件大小： | 351K |
| 代理商： | 48E30 |
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HT48E30
Rev. 0.00
19
January 12, 2004
Preliminary
READ
The READ instruction will stream out data at a specified
address on the DO. The data on DO changes during the
low-to-high edge of SK. The 8 bits data stream is pre-
ceded by a logical
0 dummy bit. Irrespective of the
condition of the EWEN or EWDS instruction, the READ
command is always valid and independent of these two
instructions. After the data word has been read the in-
ternal address will be automatically incremented by 1 al-
lowing the next consecutive data word to be read out
without entering further address data. The address will
wrap around with CS High until CS returns to Low.
EWEN/EWDS
The EWEN/EWDS instruction will enable or disable the
programming capabilities. At both the power on and
power off state the device automatically entered the dis-
able mode. Before a WRITE, ERASE, WRAL or ERAL in-
struction is given, the programming enable instruction
EWEN must be issued, otherwise the ERASE/WRITE in-
struction is invalid. After the EWEN instruction is issued,
the programming enable condition remains until power is
turned off or an EWDS instruction is given. No data can be
written into the EEPROM data memory in the program-
ming disabled state. By so doing, the internal memory data
can be protected.
ERASE
The ERASE instruction erases data at the specified ad-
dresses in the programming enable mode. After the
ERASE op-code and the specified address have been
issued, the data erase is activated by the falling edge of
CS. Since the internal auto-timing generator provides all
timing signals for the internal erase, so the SK clock is
not required. During the internal erase, we can verify the
busy/ready status if CS is high. The DO will remain low
but when the operation is over, the DO will return to high
and further instructions can be executed.
WRITE
The WRITE instruction writes data into the EEPROM
data memory at the specified addresses in the program-
ming enable mode. After the WRITE op-code and the
specified address and data have been issued, the data
writing is activated by the falling edge of CS. Since the
internal auto-timing generator provides all timing signal
for the internal writing, so the SK clock is not required.
The auto-timing write cycle includes an automatic
erase-before-write capability. So, it is not necessary to
erase data before the WRITE instruction. During the in-
ternal writing, we can verify the busy/ready status if CS
is high. The DO will remain low but when the operation is
over, the DO will return to high and further instructions
can be executed.
ERAL
The ERAL instruction erases the entire 128
8 memory
cells to a logical
1 state in the programming enable
mode. After the erase-all instruction set has been is-
sued, the data erase feature is activated by the falling
edge of CS. Since the internal auto-timing generator
provides all timing signal for the erase-all operation, so
the SK clock is not required. During the internal erase-all
operation, we can verify the busy/ready status if CS is
high. The DO will remain low but when the operation is
over, the DO will return to high and further instruction
can be executed.
WRAL
The WRAL instruction writes data into the entire 128
8
memory cells in the programming enable mode. After
the write-all instruction set has been issued, the data
writing is activated by the falling edge of CS. Since the
internal auto-timing generator provides all timing signals
for the write-all operation, so the SK clock is not re-
quired. During the internal write-all operation, we can
verify the busy/ready status if CS is high. The DO will re-
main low but when the operation is over the DO will re-
turn to high and further instruction can be executed.
EECR Control Timing Diagrams
READ
C S
S K
D O
0
D I
S t a r t b i t
1
( 1 )
t C D S
*
* A d d r e s s p o i n t e r a u t o m a t i c a l l y c y c l e s t o t h e n e x t w o r d
0
A N
A 0
D 0 D X
D X
M o d e
A N
D X
( X 8 )
A 6
D 7
1
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