参数资料
型号: 440GX
厂商: Applied Micro Circuits Corp.
英文描述: Power PC 440GX Embedded Processor
中文描述: 超出了Power PC嵌入式处理器
文件页数: 7/93页
文件大小: 794K
代理商: 440GX
440GX – Power PC 440GX Embedded Processor
AMCC
15
Revision 1.15 – August 30, 2007
Data Sheet
Universal Interrupt Controller (UIC)
Four Universal Interrupt Controllers (UIC) are available. They provide control, status, and communications
necessary between the external and internal sources of interrupts and the on-chip PowerPC processor.
Note: Processor specific interrupts (for example, page faults) do not use UIC resources.
Features include:
18 external interrupts
63 internal interrupts
Edge triggered or level-sensitive
Positive or negative active
Non-critical or critical interrupt to the on-chip processor core
Programmable interrupt priority ordering
Programmable critical interrupt vector for faster vector processing
PLB Performance Monitor
The PLB Performance Monitor (PPM) provides hardware for counting certain events associated with PLB
transactions. The contents of the counters can be read by software for analysis and enhancement of PLB
performance, or software debug. The data includes identification and duration of the events.
I2O Messaging Unit (IMU)
The IMU interfaces to the PLB as a master or slave and allows messages to be transferred between two PLB
masters (for example, the 440 CPU and PCI-X).
Features include:
Three messaging methods
- 4 Message registers—2 inbound, 2 outbound
- 2 Doorbell registers—1 inbound, 1 outbound
- 4 Circular queues—2 inbound, 2 outbound
Up to 7 different interrupt outputs generated
Support for interrupt masking
JTAG
Features include:
IEEE 1149.1 Test Access Port
IBM RISCWatch Debugger support
JTAG Boundary Scan Description Language (BSDL)
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