参数资料
型号: ZXLD1101ET5TA
厂商: Diodes Inc
文件页数: 3/16页
文件大小: 0K
描述: IC LED DRVR WHITE BCKLGT SOT23-5
产品变化通告: End of Life 16/Sept/2011
标准包装: 1
拓扑: PWM,升压(升压)
输出数: 1
内部驱动器:
类型 - 主要: 背光
类型 - 次要: 白色 LED
频率: 1MHz
电源电压: 2.5 V ~ 5.5 V
输出电压: 28V
安装类型: 表面贴装
封装/外壳: SC-74A,SOT-753
供应商设备封装: SOT-23-5
包装: 标准包装
工作温度: -40°C ~ 85°C
产品目录页面: 1478 (CN2011-ZH PDF)
其它名称: ZXLD1101ET5DKR
Last Time Buy
Closest Alternative is AP5724WUG-7
ZXLD1101
ELECTRICAL CHARACTERISTICS (at V IN = 3V , T amb = 25°C unless otherwise stated (1) )
SYMBOL
V IN
PARAMETER
Input voltage
CONDITIONS
MIN.
2.5
TYP.
MAX. UNIT
5.5
V
I IN
Supply current
Quiescent
Shutdown
V EN = V IN , I LX = 0,
Output not switching
V EN = 0V
60
100
500
A
nA
V FB
I FB
FB pin control voltage
FB pin input current
90.5
109.5
100
mV
nA
f LX
T OFF
T ON
I LXpk
Operating frequency
LX output 'OFF' time
LX output 'ON' time (2)
Switch peak current limit
L=10 H, V OUT =10V,
I OUT =20mA
L=10 H, V OUT =10V,
I OUT =20mA
350
0.35
500
320
1
5
MHz
ns
μs
mA
R LX
Switch 'On' resistance
1.5
I LX(leak)
V OUT
Switch leakage current
Controller output voltage
V LX =20V
Normal operation
1
28
μA
V
V ENH
V ENL
I ENL
I ENH
T EN(hold)
? T/T
f LPF
A LPF
? T/T
EN pin High level Input voltage
EN pin Low level Input voltage
EN pin Low level input current
EN pin High level input current
EN pin turn off delay (3)
PWM duty cycle range at ‘EN ’ input for
filtered PWM control (4)
Internal PWM low pass filter cut-off
frequency
Filter attenuation
PWM duty cycle range at ‘EN ’ input for
‘gated ’ output current control (5)
Device active
Device in shutdown
V EN =0V
V EN =V IN
V EN switched from high
to low
10kHz < f < 100kHz,
V ENH =V IN
f=30kHz
f < 1kHz, V ENH =V IN
1.5
20
0
120
4
52.5
V IN
0.4
-100
1
100
100
V
V
nA
A
μs
%
kHz
dB
%
NOTES:
(1) Production testing of the device is performed at 25°C. Functional operation of the device over a -40°C to +85°C temperature range is
guaranteed by design, characterisation and process control.
(2) Nominal 'on' time (T ONnom ) is defined by the input voltage (V IN ), coil inductance (L) and peak current (I LXpkdc ) according to the expression:
T ONnom = {I LX(pkdc ) x L/V IN } +200ns.
(3) This is the time for which the device remains active after the EN pin has been asserted low. This delay is necessary to allow the output to be
maintained during dc PWM mode operation.
(4) The minimum PWM signal frequency during this mode of operation is to ensure that the device remains active during PWM control. This
provides a continuous dc output current. For lower frequencies, the device will be gated 'on' and 'off' during PWM control.
(5) The maximum PWM signal frequency during this mode of operation should be kept as low as possible to minimise errors due to the turn-off
delay of the device (see Enable pin turn-off delay).
ISSUE 4 - JULY 2004
3
SEMICONDUCTORS
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