参数资料
| 型号： | XRT83SL314IB |
| 厂商： | Exar Corporation |
| 文件页数： | 43/83页 |
| 文件大小： | 0K |
| 描述： | IC LIU SH T1/E1/J1 14CH 304TBGA |
| 标准包装： | 27 |
| 类型： | 线路接口装置（LIU） |
| 驱动器/接收器数： | 14/14 |
| 规程： | T1，E1，J1 |
| 电源电压： | 3.135 V ~ 3.465 V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 304-LBGA |
| 供应商设备封装： | 304-TBGA（31x31） |
| 包装： | 托盘 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页当前第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页
XRT83SL314
xr
REV. 1.0.1
14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
45
5.2
Intel Mode Programmed I/O Access (Asynchronous)
If the LIU is interfaced to an Intel type P, then it should be configured to operate in the Intel mode. Intel type
Read and Write operations are described below.
Intel Mode Read Cycle
Whenever an Intel-type P wishes to read the contents of a register, it should do the following.
1. Place the address of the target register on the address bus input pins ADDR[10:0].
2. While the P is placing this address value on the address bus, the address decoding circuitry should
assert the CS pin of the LIU, by toggling it "Low". This action enables further communication between the
P and the LIU microprocessor interface block.
3. Toggle the ALE input pin "High". This step enables the address bus input drivers, within the microproces-
sor interface block of the LIU.
4. The P should then toggle the ALE pin "Low". This step causes the LIU to latch the contents of the address
bus into its internal circuitry. At this point, the address of the register has now been selected.
5. Next, the P should indicate that this current bus cycle is a Read operation by toggling the RD input pin
"Low". This action also enables the bi-directional data bus output drivers of the LIU.
6. After the P toggles the Read signal "Low", the LIU will toggle the RDY output pin "Low". The LIU does this
in order to inform the P that the data is available to be read by the P, and that it is ready for the next com-
mand.
7. After the P detects the RDY signal and has read the data, it can terminate the Read Cycle by toggling the
RD input pin "High".
NOTE: ALE can be tied “High” if this signal is not available.
The Intel Mode Write Cycle
Whenever an Intel type P wishes to write a byte or word of data into a register within the LIU, it should do the
following.
1. Place the address of the target register on the address bus input pins ADDR[10:0].
2. While the P is placing this address value on the address bus, the address decoding circuitry should
assert the CS pin of the LIU, by toggling it "Low". This action enables further communication between the
P and the LIU microprocessor interface block.
3. Toggle the ALE input pin "High". This step enables the address bus input drivers, within the microproces-
sor interface block of the LIU.
4. The P should then toggle the ALE pin "Low". This step causes the LIU to latch the contents of the address
bus into its internal circuitry. At this point, the address of the register has now been selected.
5. The P should then place the byte or word that it intends to write into the target register, on the bi-direc-
tional data bus DATA[7:0].
6. Next, the P should indicate that this current bus cycle is a Write operation by toggling the WR input pin
"Low". This action also enables the bi-directional data bus input drivers of the LIU.
7. After the P toggles the Write signal "Low", the LIU will toggle the RDY output pin "Low". The LIU does this
in order to inform the P that the data has been written into the internal register location, and that it is ready
for the next command.
NOTE: ALE can be tied “High” if this signal is not available.
The Intel Read and Write timing diagram is shown in Figure 39.
The timing specifications are shown in
相关PDF资料 |
PDF描述 |
|---|---|
| MS3101R22-23P | CONN RCPT 8POS PANEL MNT W/PINS |
| XRT75L03IVTR-F | IC LIU E3/DS3/STS-1 3CH 128LQFP |
| IDT72V3650L6BB8 | IC FIFO SS 2048X36 6NS 144-BGA |
| MS3101A22-19P | CONN RCPT 14POS FREE HNG W/PINS |
| ISL267440IUZ-T | IC INTERFACE |
相关代理商/技术参数 |
参数描述 |
|---|---|
| XRT83SL314IB-F | 功能描述:LIN 收发器 RoHS:否 制造商:NXP Semiconductors 工作电源电压: 电源电流: 最大工作温度: 封装 / 箱体:SO-8 |
| XRT83SL314IB-L | 功能描述:LIN 收发器 14 channel, SH T1/E1 LIU RoHS:否 制造商:NXP Semiconductors 工作电源电压: 电源电流: 最大工作温度: 封装 / 箱体:SO-8 |
| XRT83SL34 | 制造商:EXAR 制造商全称:EXAR 功能描述:QUAD T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR |
| XRT83SL34ES | 功能描述:外围驱动器与原件 - PCI 4 CHT1/E1 LIUSH RoHS:否 制造商:PLX Technology 工作电源电压: 最大工作温度: 安装风格:SMD/SMT 封装 / 箱体:FCBGA-1156 封装:Tray |
| XRT83SL34IV | 功能描述:时钟合成器/抖动清除器 RoHS:否 制造商:Skyworks Solutions, Inc. 输出端数量: 输出电平: 最大输出频率: 输入电平: 最大输入频率:6.1 GHz 电源电压-最大:3.3 V 电源电压-最小:2.7 V 封装 / 箱体:TSSOP-28 封装:Reel |
发布紧急采购，3分钟左右您将得到回复。