参数资料
| 型号： | XRT83L34IV |
| 厂商： | Exar Corporation |
| 文件页数： | 11/99页 |
| 文件大小： | 0K |
| 描述： | IC LIU T1/E1/J1 QUAD 128TQFP |
| 标准包装： | 72 |
| 类型： | 线路接口装置（LIU） |
| 驱动器/接收器数： | 4/4 |
| 规程： | T1，E1，J1 |
| 电源电压： | 3.135 V ~ 3.465 V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 128-LQFP |
| 供应商设备封装： | 128-TQFP（14x20） |
| 包装： | 托盘 |
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xr
XRT83L34
QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.1
16
RDY_DTACK
RXMUTE
73
O
I
Ready or DTACK Output/Receive Muting upon LOS Command Input
pin:
The exact function of this input pin depends upon whether the XRT83L34
device has been configured to operate in the HOST or Hardware Mode, as
described below.
HOST Mode Operation - READY or DTACK Output Pin:
The exact function of this input pin depends upon which mode the Micropro-
cessor Interface has been configured to operate in, as described below.
Intel-Asynchronous Mode - RDY* - Ready Output:
If the Microprocessor Interface has been configured to operate in the Intel-
Asynchronous Mode, then this output pin will function as the "active-low"
READY output.
During a READ or WRITE cycle, the Microprocessor Interface block will tog-
gle this output pin to the logic low level, ONLY when it (the Microprocessor
Interface) is ready to complete or terminate the current READ or WRITE
cycle. Once the Microprocessor has determined that this input pin has tog-
gled to the logic "low" level, then it is now safe for it to move on and execute
the next READ or WRITE cycle.
If (during a READ or WRITE cycle) the Microprocessor Interface block is
holding this output pin at a logic "high" level, then the Microprocessor is
expected to extend this READ or WRITE cycle, until it detects this output pin
being toggled to the logic low level.
Motorola-Asynchronous Mode - DTACK* - Data Transfer Acknowledge
Output:
If the Microprocessor interface has been configured to operate in the Motor-
ola-Asynchronous Mode, then this output pin will function as the "active-low"
DTACK output.
During a READ or WRITE cycle, the Microprocessor Interface block will tog-
gle this output pin to the logic low level, ONLY when it (the Microprocessor
Interface) is ready to complete or terminate the current READ or WRITE
cycle. Once the Microprocessor Interface has determined that this input pin
has toggled to the logic "low" level, then it is now safe for it to move on and
execute the next READ or WRITE cycle.
If (during a READ or WRITE cycle) the Microprocessor Interface block is
holding this output pin at a logic "HIGH" level, then the MIcroprocessor is
expected to extend this READ or WRITE cycle, until it detects this output pin
being toggled to the logic "LOW" level.
Receive Muting - Hardware mode
NOTE: Internally pulled “Low” with a 50k
resistor.
SIGNAL NAME
PIN #TYPE
DESCRIPTION
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相关代理商/技术参数 |
参数描述 |
|---|---|
| XRT83L34IV-F | 功能描述:网络控制器与处理器 IC RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流（最大值）:595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray |
| XRT83L34IVTR | 功能描述:外围驱动器与原件 - PCI RoHS:否 制造商:PLX Technology 工作电源电压: 最大工作温度: 安装风格:SMD/SMT 封装 / 箱体:FCBGA-1156 封装:Tray |
| XRT83L34IVTR-F | 功能描述:外围驱动器与原件 - PCI RoHS:否 制造商:PLX Technology 工作电源电压: 最大工作温度: 安装风格:SMD/SMT 封装 / 箱体:FCBGA-1156 封装:Tray |
| XRT83L38 | 制造商:EXAR 制造商全称:EXAR 功能描述:OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR |
| XRT83L38_07 | 制造商:EXAR 制造商全称:EXAR 功能描述:OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR |
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