参数资料
| 型号： | XC6SLX45T-2FG484I |
| 厂商： | Xilinx Inc |
| 文件页数： | 57/89页 |
| 文件大小： | 0K |
| 描述： | IC FPGA SPARTAN 6 484FGGBGA |
| 标准包装： | 60 |
| 系列： | Spartan® 6 LXT |
| LAB/CLB数： | 3411 |
| 逻辑元件/单元数： | 43661 |
| RAM 位总计： | 2138112 |
| 输入/输出数： | 296 |
| 电源电压： | 1.14 V ~ 1.26 V |
| 安装类型： | 表面贴装 |
| 工作温度： | -40°C ~ 100°C |
| 封装/外壳： | 484-BBGA |
| 供应商设备封装： | 484-FBGA |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页当前第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页
Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
DS162 (v3.0) October 17, 2011
Product Specification
60
LOCK_DLL(3)
When using the DLL alone: The time
from deassertion at the DCM’s reset
input to the rising transition at its
LOCKED output. When the DCM is
locked, the CLKIN and CLKFB
signals are in phase.
CLKIN_FREQ_DLL < 50 MHz.
–
5
–
5
–5–
5
ms
When using the DLL alone: The time
from deassertion at the DCM’s reset
input to the rising transition at its
LOCKED output. When the DCM is
locked, the CLKIN and CLKFB
signals are in phase.
CLKIN_FREQ_DLL > 50 MHz
–
0.60
–
0.60
–
0.60
–
0.60
ms
Delay Lines
DCM_DELAY_STEP(5)
Finest delay resolution, averaged
over all steps.
10
40
10
40
10
40
10
40
ps
Notes:
1.
2.
Indicates the maximum amount of output jitter that the DCM adds to the jitter on the CLKIN input.
3.
For optimal jitter tolerance and faster LOCK time, use the CLKIN_PERIOD attribute.
4.
Some jitter and duty-cycle specifications include 1% of input clock period or 0.01 UI. For example, this data sheet specifies a maximum jitter of
±(1% of CLKIN period + 150 ps). Assuming that the CLKIN frequency is 100 MHz, the equivalent CLKIN period is 10 ns. Since 1% of 10 ns is 0.1 ns
or 100 ps, the maximum jitter is ±(100 ps + 150 ps) = ±250 ps.
5.
A typical delay step size is 23 ps.
6.
The timing analysis tools use the CLK_FEEDBACK = 1X condition for the CLKIN_CLKFB_PHASE value (reported as phase error). When using
CLK_FEEDBACK = 2X, add 100 ps to the phase error for the CLKIN_CLKFB_PHASE value (as shown in this table).
Table 55: Recommended Operating Conditions for the Digital Frequency Synthesizer (DFS)(1)
Symbol
Description
Speed Grade
Units
-3
-3N
-2
-1L
Min
Max
Min
Max
Min
Max
Min
Max
Input Frequency Ranges(2)
CLKIN_FREQ_FX
Frequency for the CLKIN input. Also
described as FCLKIN.
0.5
375(3)
0.5
375(3)
0.5
333(3)
0.5
200(3) MHz
Input Clock Jitter Tolerance(4)
CLKIN_CYC_JITT_FX_LF
Cycle-to-cycle jitter at the CLKIN input,
based on CLKFX output frequency:
FCLKFX < 150 MHz.
–
±300–±300–
±300–±300
ps
CLKIN_CYC_JITT_FX_HF Cycle-to-cycle jitter at the CLKIN input,
based on CLKFX output frequency:
FCLKFX > 150 MHz.
–
±150–±150–
±150–±150
ps
CLKIN_PER_JITT_FX
Period jitter at the CLKIN input.
–
±1
–
±1
–
±1
–
±1
ns
Notes:
1.
DFS specifications apply when using either of the DFS outputs (CLKFX or CLKFX180).
2.
When using both DFS and DLL outputs on the same DCM, follow the more restrictive CLKIN_FREQ_DLL specifications in Table 53.
3.
The CLKIN_DIVIDE_BY_2 attribute increases the effective input frequency range. When set to TRUE, the input clock frequency is divided by two as
it enters the DCM. Input clock frequencies for the clock buffer being used can be increased up to the FMAX (see Table 48 and Table 49 for BUFG and
BUFIO2 limits).
4.
CLKIN input jitter beyond these limits can cause the DCM to lose LOCK.
Table 54: Switching Characteristics for the Delay-Locked Loop (DLL)(1) (Cont’d)
Symbol
Description
Speed Grade
Units
-3
-3N
-2
-1L
Min
Max
Min
Max
Min
Max
Min
Max
相关PDF资料 |
PDF描述 |
|---|---|
| XC6SLX45T-2FGG484I | IC FPGA SPARTAN 6 43K 484FGGBGA |
| 25LC080D-E/ST | IC SRL EEPROM 1KX8 2.5V 8-TSSOP |
| 25LC080C-E/MS | IC SRL EEPROM 1KX8 2.5V 8-MSOP |
| XC6SLX45T-N3CSG484I | IC FPGA SPARTAN-6 484CSBGA |
| 25AA320AXT-I/ST | IC EEPROM 32KBIT 10MHZ 8TSSOP |
相关代理商/技术参数 |
参数描述 |
|---|---|
| XC6SLX45T-2FGG484C | 功能描述:IC FPGA SPARTAN 6 43K 484FGGBGA RoHS:是 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:Spartan® 6 LXT 标准包装:60 系列:XP LAB/CLB数:- 逻辑元件/单元数:10000 RAM 位总计:221184 输入/输出数:244 门数:- 电源电压:1.71 V ~ 3.465 V 安装类型:表面贴装 工作温度:0°C ~ 85°C 封装/外壳:388-BBGA 供应商设备封装:388-FPBGA（23x23） 其它名称:220-1241 |
| XC6SLX45T-2FGG484CES9982 | 制造商:Xilinx 功能描述: |
| XC6SLX45T-2FGG484I | 功能描述:IC FPGA SPARTAN 6 43K 484FGGBGA RoHS:是 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:Spartan® 6 LXT 标准包装:40 系列:Spartan® 6 LX LAB/CLB数:3411 逻辑元件/单元数:43661 RAM 位总计:2138112 输入/输出数:358 门数:- 电源电压:1.14 V ~ 1.26 V 安装类型:表面贴装 工作温度:-40°C ~ 100°C 封装/外壳:676-BGA 供应商设备封装:676-FBGA（27x27） |
| XC6SLX45T-2FGG676C | 制造商:Xilinx 功能描述: |
| XC6SLX45T-2FGG676I | 制造商:Xilinx 功能描述: |
发布紧急采购，3分钟左右您将得到回复。