参数资料
型号: XA3SD1800A-4FGG676Q
厂商: Xilinx Inc
文件页数: 31/58页
文件大小: 0K
描述: SPARTAN-3ADSP FPGA 1800K 676FBGA
产品培训模块: Extended Spartan 3A FPGA Family
标准包装: 40
系列: Spartan®-3A DSP XA
LAB/CLB数: 4160
逻辑元件/单元数: 37440
RAM 位总计: 1548288
输入/输出数: 519
门数: 1800000
电源电压: 1.14 V ~ 1.26 V
安装类型: 表面贴装
工作温度: -40°C ~ 125°C
封装/外壳: 676-BGA
供应商设备封装: 676-FBGA(27x27)
配用: 122-1574-ND - KIT DEVELOPMENT SPARTAN 3ADSP
XA Spartan-3A DSP Automotive FPGA Family Data Sheet
DS705 (v2.0) April 18, 2011
Product Specification
37
Configurable Logic Block Timing
Table 30: CLB (SLICEM) Timing
Symbol
Description
Speed Grade: -4
Units
Min
Max
Clock-to-Output Times
TCKO
When reading from the FFX (FFY) Flip-Flop, the time from the active transition
at the CLK input to data appearing at the XQ (YQ) output
–0.68
ns
Setup Times
TAS
Time from the setup of data at the F or G input to the active transition at the
CLK input of the CLB
0.36
–ns
TDICK
Time from the setup of data at the BX or BY input to the active transition at the
CLK input of the CLB
1.88
–ns
Hold Times
TAH
Time from the active transition at the CLK input to the point where data is last
held at the F or G input
0.00
–ns
TCKDI
Time from the active transition at the CLK input to the point where data is last
held at the BX or BY input
0.00
–ns
Clock Timing
TCH
The High pulse width of the CLB’s CLK signal
0.75
–ns
TCL
The Low pulse width of the CLK signal
0.75
–ns
FTOG
Toggle frequency (for export control)
0
667
MHz
Propagation Times
TILO
The time it takes for data to travel from the CLB’s F (G) input to the X (Y) output
–0.71
ns
Set/Reset Pulse Width
TRPW_CLB
The minimum allowable pulse width, High or Low, to the CLB’s SR input
1.61
–ns
Notes:
1.
The numbers in this table are based on the operating conditions set forth in Table 8.
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