参数资料
型号: UPC2758TB-A
厂商: CEL
文件页数: 2/5页
文件大小: 0K
描述: IC MMIC DWN-CNVRTR SOT-363
产品目录绘图: NE69, UP Series
标准包装: 1
系列: UPC2758TB
RF 型: 手机
频率: 100MHz ~ 2GHz
混频器数目: 1
增益: 19dB
噪音数据: 9dB
次要属性: 降频变频器
电流 - 电源: 14.8mA
电源电压: 2.7 V ~ 3.3 V
包装: 散装
封装/外壳: 6-TSSOP,SC-88,SOT-363
供应商设备封装: 6-SuperMiniMold
产品目录页面: 577 (CN2011-ZH PDF)
UPC2757TB, UPC2758TB
ABSOLUTE MAXIMUM RATINGS 1 (T A = 25 ° C)
TEST CIRCUIT/BLOCK DIAGRAM
SYMBOLS
V CC, V PS
P T
PARAMETERS
Supply Voltage
Total Power Dissipation 2
UNITS
V
mW
RATINGS
5.5
200
UPC2757TB, UPC2758TB
V PS
T OP
T STG
Operating Temperature
Storage Temperature
° C
° C
-40 to +85
-55 to +150
LO In
3
4
V CC
Notes:
1. Operation in excess of any one of these parameters may result
in permanent damage.
2. Mounted on a 50 x 50 x 1.6 mm epoxy glass PWB (T A = +85 ° C).
RECOMMENDED
OPERATING CONDITIONS
RF In
2
1
5
6
IF Out
SYMBOLS
PARAMETERS
UNITS
MIN
TYP MAX
V CC
T OP
P LO
Supply Voltage
Operating Temperature
LO Input Level
V
° C
dBm
2.7
-40
-15
3.0
+25
-10
3.3
+85
0
All Capacitors 0.1 μ F
PIN DESCRIPTION
Pin
No.
Pin
Name
Applied
Voltage
Pin
Voltage
Description
Internal
Equivalent Circuit
(V)
(V)
1
RF IN
1.2
Signal input pin to double balanced mixer.
V CC
This pin must be coupled to the signal source
with a blocking capacitor.
From
To IF
Amp
LO
1
2
GND
0
Ground pin. This pin should be connected to
system ground with minimum inductance.
Ground pattern on the board should be formed as
wide as possible.
V CC
3
LO IN
1.3
LO input pin. The LO buffer is designed as a
Mixer
differential amplifier. Recommended input level
is -15 to 0 dBm.
3
4
V PS
V CC / GND
Power save control pin can control the On/Sleep
V CC
state with bias as follows:
V PS (V) STATE
≥ 2.5 ON
0 to 0.5 SLEEP
Rise time/fall time using this pin is approximately
10 μ s.
4
5
V CC
2.7 to 3.3
Power supply pin. This pin should be externally
equipped with a bypass capacitor to minimize
ground impedance.
6
IF OUT
1.7
Output of single-ended push-pull IF buffer amplifier.
This is an emitter-follower output with low impedance.
This pin must be coupled to the next stage with a
blocking capacitor.
6
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