参数资料
型号: THS1209IDAG4
厂商: TEXAS INSTRUMENTS INC
元件分类: ADC
英文描述: 2-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO32
封装: GREEN, PLASTIC, TSSOP-32
文件页数: 20/33页
文件大小: 312K
代理商: THS1209IDAG4
THS1209
SLAS288B – JULY 2000 – REVISED DECEMBER 2002
www.ti.com
27
Write Timing (using R/W, CS0-controlled)
Figure 32 shows the write-timing behavior when the WR(R/W) input is programmed as a combined read-write input
R/W. The RD input has to be tied to high-level in this configuration. This timing is called CS0-controlled because CS0
is the last external signal of CS0, CS1, and R/W which becomes valid. The writing to the THS1209 can be performed
irrespective of the conversion clock signal CONV_CLK.
D(0–11)
10%
90%
tw(CS)
tsu(R/W)
th(R/W)
tsu
th
RD
R/W
CS1
CS0
Figure 32. Write Timing Diagram Using R/W (CS0-controlled)
Write Timing Parameter (CSO-controlled)
PARAMETER
MIN
TYP
MAX
UNIT
tsu(R/W)
Setup time, R/W stable to last CS valid
0
ns
tsu
Setup time, data valid to first CS invalid
5
ns
th
Hold time, first CS invalid to data invalid
2
ns
th(R/W)
Hold time, first CS invalid to R/W change
5
ns
tw(CS)
Pulse duration, CS active
10
ns
相关PDF资料
PDF描述
THS1215CDWRG4 1-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO28
THS1215IDWRG4 1-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO28
THS1215CPWRG4 1-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO28
THS1215CDW 1-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO28
THS1215CPW 1-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO28
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