参数资料
型号: SST25VF010A-33-4I-ZAE
厂商: Microchip Technology
文件页数: 7/28页
文件大小: 0K
描述: IC FLASH SER 1MB 33MHZ SPI 8CSP
标准包装: 3,000
系列: SST25
格式 - 存储器: 闪存
存储器类型: FLASH
存储容量: 1M (128K x 8)
速度: 33MHz
接口: SPI 串行
电源电压: 2.7 V ~ 3.6 V
工作温度: -40°C ~ 85°C
封装/外壳: 8-UFBGA,CSPBGA
供应商设备封装: 8-CSP
包装: 管件
1 Mbit SPI Serial Flash
A Microchip Technology Company
SST25VF010A
Data Sheet
Status Register
The software status register provides status on whether the flash memory array is available for any
Read or Write operation, whether the device is Write enabled, and the state of the memory Write pro-
tection. During an internal Erase or Program operation, the status register may be read only to deter-
mine the completion of an operation in progress. Table 4 describes the function of each bit in the
software status register.
Table 4: Software Status Register
Default at
Bit
0
Name
BUSY
Function
1 = Internal Write operation is in progress
Power-up
0
Read/Write
R
0 = No internal Write operation is in progress
1
WEL
1 = Device is memory Write enabled
0
R
0 = Device is not memory Write enabled
2
3
4:5
6
BP0
BP1
RES
AAI
Indicate current level of block write protection (See Table 5)
Indicate current level of block write protection (See Table 5)
Reserved for future use
Auto Address Increment Programming status
1
1
0
0
R/W
R/W
N/A
R
1 = AAI programming mode
0 = Byte-Program mode
7
BPL
1 = BP1, BP0 are read-only bits
0
R/W
0 = BP1, BP0 are read/writable
T4.0 25081
Busy
The Busy bit determines whether there is an internal Erase or Program operation in progress. A “1” for
the Busy bit indicates the device is busy with an operation in progress. A “0” indicates the device is
ready for the next valid operation.
Write Enable Latch (WEL)
The Write-Enable-Latch bit indicates the status of the internal memory Write Enable Latch. If the
Write-Enable-Latch bit is set to “1”, it indicates the device is Write enabled. If the bit is set to “0” (reset),
it indicates the device is not Write enabled and does not accept any memory Write (Program/Erase)
commands. The Write-Enable-Latch bit is automatically reset under the following conditions:
?
?
?
?
?
?
?
Power-up
Write-Disable (WRDI) instruction completion
Byte-Program instruction completion
Auto Address Increment (AAI) programming reached its highest memory address
Sector-Erase instruction completion
Block-Erase instruction completion
Chip-Erase instruction completion
?2011 Silicon Storage Technology, Inc.
7
S725081A
10/11
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