参数资料
型号: SI5367/68-EVB
厂商: Silicon Laboratories Inc
文件页数: 67/80页
文件大小: 0K
描述: BOARD EVAL FOR SI5367/68
标准包装: 1
主要目的: 计时,时钟发生器
已用 IC / 零件: SI5367,SI5368
已供物品: 板,线缆,CD,文档
Si5367
Rev. 0.5
7
Output Drive Current
(CMOS driving into
CKOVOL for output low
or CKOVOH for output
high. CKOUT+ and
CKOUT– shorted
externally)
CKOIO
ICMOS[1:0] = 11
VDD =1.8 V
—7.5
mA
ICMOS[1:0] = 10
VDD =1.8 V
—5.5
mA
ICMOS[1:0] = 01
VDD =1.8 V
—3.5
mA
ICMOS[1:0] = 00
VDD =1.8 V
—1.75
mA
ICMOS[1:0] = 11
VDD =3.3 V
—32
mA
ICMOS[1:0] = 10
VDD =3.3 V
—24
mA
ICMOS[1:0] = 01
VDD =3.3 V
—16
mA
ICMOS[1:0] = 00
VDD =3.3 V
—8
mA
2-Level LVCMOS Input Pins
Input Voltage Low
VIL
VDD =1.71V
0.5
V
VDD =2.25V
0.7
V
VDD =2.97V
0.8
V
Input Voltage High
VIH
VDD =1.89V
1.4
V
VDD =2.25V
1.8
V
VDD =3.63V
2.5
V
Table 2. DC Characteristics (Continued)
(VDD = 1.8 ± 5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Notes:
1. Current draw is independent of supply voltage.
2. The LVPECL and CMOS output formats draw more current than either LVDS or CML; however, there are restrictions in
the allowed output format pin settings so that the maximum power dissipation for the TQFP devices is limited when
they are operated at 3.3 V. When there are four enabled LVPECL or CMOS outputs, the fifth output must be disabled.
When there are five enabled outputs, there can be no more than three outputs that are either LVPECL or CMOS.
3. No under- or overshoot is allowed.
4. LVPECL outputs require nominal VDD
≥ 2.5 V.
5. LVPECL, CML, LVDS and low-swing LVDS measured with Fo = 622.08 MHz.
6. This is the amount of leakage that the 3-Level inputs can tolerate from an external driver. See Si53xx Family Reference
Manual for more details.
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