参数资料
型号: SI5322/23-EVB
厂商: Silicon Laboratories Inc
文件页数: 9/24页
文件大小: 0K
描述: BOARD EVAL FOR SI5322/23
标准包装: 1
主要目的: 计时,时钟发生器
已用 IC / 零件: SI5322,SI5323
已供物品: 板,线缆,CD,文档
Si5322
Rev. 0.51
17
33
30
SFOUT0
SFOUT1
I
3-Level
Signal Format Select.
Three level inputs that select the output signal format (com-
mon mode voltage and differential swing) for both CKOUT1
and CKOUT2. Valid settings include LVPECL, LVDS, and
CML. Also includes selections for CMOS mode, tristate
mode, and tristate/sleep mode.
CMOS outputs do not support Bypass Mode.
These pins have both weak pull-ups and weak pull-downs
and default to M.
Some designs may require an external resistor voltage
divider when driven by an active device that will tri-state.
34
35
CKOUT2–
CKOUT2+
OMulti
Clock Output 2.
Differential output clock with a frequency selected from a
table of values. Output signal format is selected by SFOUT
pins. Output is differential for LVPECL, LVDS, and CML
compatible modes. For CMOS format, both output pins drive
identical single-ended clock outputs.
29
28
CKOUT1–
CKOUT1+
OMulti
Clock Output 1.
Differential output clock with a frequency selected from a
table of values. Output signal format is selected by SFOUT
pins. Output is differential for LVPECL, LVDS, and CML
compatible modes. For CMOS format, both output pins drive
identical single-ended clock outputs.
7, 18, 36
NC
No Connect.
These pins must be left unconnected for normal operation.
GND PAD
GND
Supply
Ground Pad.
The ground pad must provide a low thermal and electrical
impedance to a ground plane.
Table 9. Si5322 Pin Descriptions (Continued)
Pin #
Pin Name
I/O
Signal Level
Description
SFOUT[1:0]
Signal Format
HH
Reserved
HM
LVDS
HL
CML
MH
LVPECL
MM
Reserved
ML
LVDS—Low Swing
LH
CMOS
LM
Disabled
LL
Reserved
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