参数资料
型号: SI5319-EVB
厂商: Silicon Laboratories Inc
文件页数: 45/50页
文件大小: 0K
描述: BOARD EVALUATION SI5319
标准包装: 1
主要目的: 计时,时钟乘法器
嵌入式: 否
已用 IC / 零件: SI5319
主要属性: 1 输入,1 输出
次要属性: CML,CMOS,LVDS,LVPECL
已供物品: 板,CD,文档
Si5319
Rev. 1.0
5
Table 2. DC Characteristics
(VDD = 1.8 ± 5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Supply Current1
IDD
LVPECL Format
622.08 MHz Out
—
217
243
mA
CMOS Format
19.44 MHz Out
—
194
220
mA
Disable Mode
—
165
—
mA
CKIN Input Pin2
Input Common Mode
Voltage (Input Thresh-
old Voltage)
VICM
1.8 V ± 5%
0.9
—
1.4
V
2.5 V ± 10%
1
—
1.7
V
3.3 V ± 10%
1.1
—
1.95
V
Input Resistance
CKNRIN
Single-ended
20
40
60
k
Single-Ended Input
Voltage Swing
(See Absolute Specs)
VISE
fCKIN <212.5 MHz
0.2
—
VPP
fCKIN >212.5 MHz
0.25
—
VPP
Differential Input
Voltage Swing
(See Absolute Specs)
VID
fCKIN <212.5 MHz
0.2
—
VPP
fCKIN >212.5 MHz
0.25
—
VPP
Output Clock (CKOUT)3
Common Mode
CKOVCM
LVPECL 100
load
line-to-line
VDD –1.42
—
VDD –1.25
V
Differential Output
Swing
CKOVD
LVPECL 100
load
line-to-line
1.1
—
1.9
VPP
Single Ended Output
Swing
CKOVSE
LVPECL 100
load
line-to-line
0.5
—
0.93
VPP
Differential Output
Voltage
CKOVD
CML 100
load line-to-
line
350
425
500
mVPP
Notes:
1.
Current draw is independent of supply voltage.
2.
No under- or overshoot is allowed.
3.
LVPECL outputs require nominal VDD ≥ 2.5 V.
4.
This is the amount of leakage that the 3-level inputs can tolerate from an external driver. See Si53xx Family
Reference Manual for more details.
5.
LVPECL, CML, LVDS and low-swing LVDS measured with Fo = 622.08 MHz.
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