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参数资料
| 型号： | S25FL004D |
| 厂商： | Spansion Inc. |
| 英文描述： | 4 Megabit CMOS 3.0 Volt Flash Memory with 50 Mhz SPI Bus Interface |
| 中文描述： | 4兆位的CMOS闪存3.0伏，50赫兹的SPI总线接口 |
| 文件页数： | 6/36页 |
| 文件大小： | 724K |
| 代理商： | S25FL004D |
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14
S25FL Family (Serial Peripheral Interface) S25FL004D
S25FL004D_00A0 June 28, 2004
Ad va n c e
In f o rm a t i o n
Write Enable (WREN)
The Write Enable (WREN) instruction (Figure 4) sets the Write Enable Latch (WEL)
bit. The Write Enable Latch (WEL) bit must be set prior to every Page Program
(PP), Erase (SE or BE) and Write Status Register (WRSR) instruction. The Write
Enable (WREN) instruction is entered by driving Chip Select (CS#) Low, sending
the instruction code, and then driving Chip Select (CS#) High.
Figure 4. Write Enable (WREN) Instruction Sequence
Write Disable (WRDI)
The Write Disable (WRDI) instruction (Figure 5) resets the Write Enable Latch
(WEL) bit. The Write Disable (WRDI) instruction is entered by driving Chip Select
(CS#) Low, sending the instruction code, and then driving Chip Select (CS#)
High.
The Write Enable Latch (WEL) bit is reset under the following conditions:
Power-up
Write Disable (WRDI) instruction completion
Write Status Register (WRSR) instruction completion
Page Program (PP) instruction completion
Sector Erase (SE) instruction completion
Bulk Erase (BE) instruction completion
Figure 5. Write Disable (WRDI) Instruction Sequence
CS#
SCK
SI
SO
High Impedance
Instruction
01
2 3
4 5 67
0 1 2 34 5 6 7
SCK
SI
SO
High Impedance
Instruction
CS#
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PDF描述 |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| S25FL004D0FMFI | 制造商:Spansion 功能描述: |
| S25FL004D0LMAI011 | 制造商:SPANSION 制造商全称:SPANSION 功能描述:4 Megabit CMOS 3.0 Volt Flash Memory with 50 Mhz SPI Bus Interface |
| S25FL004D0LMAI013 | 制造商:SPANSION 制造商全称:SPANSION 功能描述:4 Megabit CMOS 3.0 Volt Flash Memory with 50 Mhz SPI Bus Interface |
| S25FL004D0LMFI011 | 制造商:SPANSION 制造商全称:SPANSION 功能描述:4 Megabit CMOS 3.0 Volt Flash Memory with 50 Mhz SPI Bus Interface |
| S25FL004D0LMFI013 | 制造商:SPANSION 制造商全称:SPANSION 功能描述:4 Megabit CMOS 3.0 Volt Flash Memory with 50 Mhz SPI Bus Interface |
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