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参数资料
| 型号： | MPC8560VT667LC |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 36/36页 |
| 文件大小： | 0K |
| 描述： | IC MPU POWERQUICC III 783-FCPBGA |
| 标准包装： | 36 |
| 系列： | MPC85xx |
| 处理器类型： | 32-位 MPC85xx PowerQUICC III |
| 速度： | 667MHz |
| 电压： | 1.2V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 784-BBGA，FCBGA |
| 供应商设备封装： | 783-FCPBGA（29x29） |
| 包装： | 托盘 |
| 配用： | MPC8560ADS-BGA-ND - BOARD APPLICATION DEV 8560 |
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MOTOROLA
MPC8560 PowerQUICC III
9
Integrated Communications Processor Product Brief
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
e500 Core Overview
The following is a brief list of some of the key features of the e500 core complex:
Implements full Book E 32-bit architecture
Implements additional instructions, registers, and interrupts defined by APUs. The SPE provides an
extensive instruction set for 64-bit vector integer, single-precision floating-point, and fractional
operations. The SPFP APU provides scalar (32-bit) single-precision, floating-point instructions.
NOTE
The SPE APU and SPFP APU functionality will be implemented in the
MPC8540, the MPC8560 and in their derivatives (that is, in all
PowerQUICC III devices). However, these instructions will not be
supported in devices subsequent to PowerQUICC III. Motorola strongly
recommends that use of these instructions be confined to libraries and
device drivers. Customer software that uses SPE or SPFP APU
instructions at the assembly level or that uses SPE intrinsics will require
rewriting for upward compatibility with next-generation PowerQUICC
devices.
Motorola offers a lib_moto_e500 library that uses SPE and SPFP APU
instructions. Motorola will also provide future libraries to support next
generation PowerQUICC devices.
L1 cache structure
— 32-Kbyte, 32-byte line, eight-way set-associative instruction cache
— 32-Kbyte, 32-byte line, eight-way set-associative data cache
— 1.5-cycle cache array access, 3-cycle load-to-use latency
— Pseudo-LRU replacement algorithm
— Copy-back data cache
Dual-dispatch superscalar
Precise exception handling
Seven-stage pipeline control
Instruction unit
— Twelve-entry instruction queue
— Full hardware detection of interlocks
— Dispatch up to two instructions per cycle
— Dispatch serialization control
— Register dependency resolution and renaming
Branch unit (BU)
— Dynamic branch prediction
— Two-entry branch instruction queue (BIQ)
— Executes all branch and CR logical instruction
Completion unit
— As many as 14 instructions allowed in 14-entry completion queue
— In-order retirement of up to two instructions per cycle
— Completion and refetch serialization control
— Synchronization for all instruction flow changes—interrupts and mispredicted branches
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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