参数资料
型号: MPC8548EVTAQGB
厂商: Freescale Semiconductor
文件页数: 36/151页
文件大小: 0K
描述: IC MPU PWRQUICC III 783FCPBGA
产品培训模块: MPC8548 PowerQUICC III Processors
标准包装: 1
系列: MPC85xx
处理器类型: 32-位 MPC85xx PowerQUICC III
速度: 1.0GHz
电压: 1.1V
安装类型: 表面贴装
封装/外壳: 783-BBGA,FCBGA
供应商设备封装: 783-FCPBGA(29x29)
包装: 托盘
MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 9
130
Freescale Semiconductor
Clocking
20 Clocking
This section describes the PLL configuration of the device. Note that the platform clock is identical to the
core complex bus (CCB) clock.
20.1
Clock Ranges
Table 75 through Table 77 provide the clocking specifications for the processor cores and Table 78,
through Table 80 provide the clocking specifications for the memory bus.
Table 75. Processor Core Clocking Specifications (MPC8548E and MPC8547E)
Characteristic
Maximum Processor Core Frequency
Unit
Notes
1000 MHz
1200 MHz
1333 MHz
Min
Max
Min
Max
Min
Max
e500 core processor frequency
800
1000
800
1200
800
1333
MHz
1, 2
Notes:
1. Caution: The CCB to SYSCLK ratio and e500 core to CCB ratio settings must be chosen such that the resulting SYSCLK
frequency, e500 (core) frequency, and CCB frequency do not exceed their respective maximum or minimum operating
2.)The minimum e500 core frequency is based on the minimum platform frequency of 333 MHz.
Table 76. Processor Core Clocking Specifications (MPC8545E)
Characteristic
Maximum Processor Core Frequency
Unit
Notes
800 MHz
1000 MHz
1200 MHz
Min
Max
Min
Max
Min
Max
e500 core processor frequency
800
1000
800
1200
MHz
1, 2
Notes:
1. Caution: The CCB to SYSCLK ratio and e500 core to CCB ratio settings must be chosen such that the resulting SYSCLK
frequency, e500 (core) frequency, and CCB frequency do not exceed their respective maximum or minimum operating
2.)The minimum e500 core frequency is based on the minimum platform frequency of 333 MHz.
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