参数资料
型号: MPC8540PXAQFC
厂商: Freescale Semiconductor
文件页数: 64/104页
文件大小: 0K
描述: MPU POWERQUICC III 783FCPBGA
标准包装: 36
系列: MPC85xx
处理器类型: 32-位 MPC85xx PowerQUICC III
速度: 1.0GHz
电压: 1.3V
安装类型: 表面贴装
封装/外壳: 784-BBGA,FCBGA
供应商设备封装: 783-FCPBGA(29x29)
包装: 托盘
MPC8540 Integrated Processor Hardware Specifications, Rev. 4.1
62
Freescale Semiconductor
RapidIO
13.3.2 RapidIO Receiver AC Timing Specifications
The RapidIO receiver AC timing specifications are provided in Table 50. A receiver shall comply with the
specifications for each data rate/frequency for which operation of the receiver is specified. Unless
otherwise specified, these specifications are subject to the following conditions.
The specifications apply over the supply voltage and ambient temperature ranges specified by the
device vendor.
The specifications apply for any combination of data patterns on the data signals.
The specifications apply over the receiver common mode and differential input voltage ranges.
Clock specifications apply only to clock signals.
Data specifications apply only to data signals (FRAME, D[0:7])
Table 50. RapidIO Receiver AC Timing Specifications—500 Mbps Data Rate
Characteristic
Symbol
Range
Unit
Notes
Min
Max
Duty cycle of the clock input
DC
47
53
%
1, 5
Data valid
DV
1080
ps
2
Allowable static skew between any two data inputs
within a 8-/9-bit group
tDPAIR
380
ps
3
Allowable static skew of data inputs to associated clock
tSKEW,PAIR
–300
300
ps
4
Notes:
1.Measured at VID = 0 V.
2.Measured using the RapidIO receive mask shown in Figure 40.
3.See Figure 43.
5.Guaranteed by design.
Table 51. RapidIO Receiver AC Timing Specifications—750 Mbps Data Rate
Characteristic
Symbol
Range
Unit
Notes
Min
Max
Duty cycle of the clock input
DC
47
53
%
1, 5
Data valid
DV
600
ps
2
Allowable static skew between any two data inputs
within a 8-/9-bit group
tDPAIR
—400
ps
3
Allowable static skew of data inputs to associated clock
tSKEW,PAIR
–267
267
ps
4
Notes:
1.Measured at VID = 0 V.
2.Measured using the RapidIO receive mask shown in Figure 40.
5.Guaranteed by design.
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