参数资料
型号: MMA6527KWR2
厂商: Freescale Semiconductor
文件页数: 49/56页
文件大小: 0K
描述: SENSOR XY-AXIS 120/120G
产品变化通告: Reel Size Change 15/Dec/2011
标准包装: 1,000
轴: X,Y
加速范围: ±120g
灵敏度: 16 LSB/g
电源电压: 3.13 V ~ 5.25 V
输出类型: SPI
接口: SPI
安装类型: 表面贴装
封装/外壳: 16-QFN 裸露焊盘
供应商设备封装: 16-QFN-EP(6x6)
4.4
Register Access Operations
Two types of register access operations are supported; register write, and register read. Register access operations are initi-
ated when the acceleration bit (A) of the command message is set to a logic ‘0’. The operation to be performed is indicated by
the Access Selection bit (AX) of the command message.
Access Selection Bit (AX)
0
1
Operation
Register Read
Register Write
Register Access operations include a parity bit (P). Odd parity is employed. The number of logic ‘1’ bits in the Register Access
operation must be an odd number.
4.4.1
Register Write Request
During a register write request, bits 12 through 8 contain a five-bit address, and bits 7 through 0 contain the data value to be
written. Writable registers are defined in Table 3 .
The response to a register write operation is shown in Table 30 . The response is transmitted on the next SPI message if and
only if all of the following conditions are met:
? No SPI Error is detected (Reference Section 4.5.1 )
? No MISO Error is detected (Reference Section 4.5.2 )
? The ENDINIT bit is cleared (Reference Section 3.1.6.3 )
– This applies to all registers with the exception of the DEVCTL register (Only Bits 6 and 7 can be modified)
? No Invalid Register Request is detected (Reference Section 4.5.3.2 )
If the above conditions are met, the device responds to the register write request as shown in Table 30 . Otherwise, the device
Responds as specified in Section 4.5 .
Register write operations do not occur internally until the transfer during which they are requested has been completed. In the
event that a SPI Error is detected during a register write transfer, the write operation is not completed.
4.4.2
Register Read Request
During a register read request, bits 12 through 8 contain the five-bit address for the register to be read. Bits 7 through 0 must
be logic ‘0’. Readable registers are defined in Table 3 .
The response to a register read operation is shown in Table 30 . The response is transmitted on the next SPI message if and
only if all of the following conditions are met:
? No SPI Error is detected (Reference Section 4.5.1 )
? No MISO Error is detected (Reference Section 4.5.2 )
? No Invalid Register Request is detected (Reference Section 4.5.3.2 )
If the above conditions are met, the device responds to the register read request as shown in Table 30 . Otherwise, the device
responds as specified in Section 4.5 .
MMA65xx
Sensor
Freescale Semiconductor, Inc.
49
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