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| 型号： | MCF52236CAF50 |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 36/55页 |
| 文件大小： | 0K |
| 描述： | IC MCU 32BIT 256K FLASH 80-LQFP |
| 标准包装： | 90 |
| 系列： | MCF5223x |
| 核心处理器： | Coldfire V2 |
| 芯体尺寸： | 32-位 |
| 速度： | 50MHz |
| 连通性： | 以太网，I²C，SPI，UART/USART |
| 外围设备： | DMA，LVD，POR，PWM，WDT |
| 输入/输出数： | 56 |
| 程序存储器容量： | 256KB（256K x 8） |
| 程序存储器类型： | 闪存 |
| RAM 容量： | 32K x 8 |
| 电压 - 电源 (Vcc/Vdd)： | 3 V ~ 3.6 V |
| 数据转换器： | A/D 8x12b |
| 振荡器型： | 内部 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 80-LQFP |
| 包装： | 托盘 |
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Electrical Characteristics
MCF52235 ColdFire Microcontroller Data Sheet, Rev. 10
Freescale Semiconductor
41
2.9.1
Equivalent Circuit for ADC Inputs
Figure 10-17 shows the ADC input circuit during sample and hold. S1 and S2 are always open/closed at the same time that S3
is closed/open. When S1/S2 are closed and S3 is open, one input of the sample and hold circuit moves to (VREFH-VREFL)/2,
while the other charges to the analog input voltage. When the switches are flipped, the charge on C1 and C2 are averaged via
S3, with the result that a single-ended analog input is switched to a differential voltage centered about (VREFH-VREFL)/2. The
switches switch on every cycle of the ADC clock (open one-half ADC clock, closed one-half ADC clock). There are additional
capacitances associated with the analog input pad, routing, etc., but these do not filter into the S/H output voltage, as S1 provides
isolation during the charge-sharing phase. One aspect of this circuit is that there is an ongoing input current, which is a function
of the analog input voltage, VREF, and the ADC clock frequency.
fADIC
ADC internal clock
0.1
—
5.0
MHz
RAD
Conversion range
VREFL
—VREFH
V
tADPU
ADC power-up time5
—6
13
tAIC cycles
6
tREC
Recovery from auto standby
—
0
1
tAIC cycles
tADC
Conversion time
—
6
—
tAIC cycles
tADS
Sample time
—
1
—
tAIC cycles
CADI
Input capacitance
—
See Figure 12
—pF
XIN
Input impedance
—
See Figure 12
—W
IADI
Input injection current7, per pin
—
3
mA
IVREFH
VREFH current
—
0
—
mA
VOFFSET
Offset voltage internal reference
—
11
15
mV
EGAIN
Gain error (transfer path)
.99
1
1.01
—
VOFFSET
Offset voltage external reference
—
3—
mV
SNR
Signal-to-noise ratio
—
62 to 66
—
dB
THD
Total harmonic distortion
—
–75
—
dB
SFDR
Spurious free dynamic range
—
75
—
dB
SINAD
Signal-to-noise plus distortion
—
65
—
dB
ENOB
Effective number OF bits
9.1
10.6
—
Bits
1 All measurements were made at V
DD = 3.3V, VREFH = 3.3V, and VREFL = ground
2 INL measured from V
IN = VREFL to VIN = VREFH
3 LSB = Least Significant Bit
4 INL measured from V
IN = 0.1VREFH to VIN = 0.9VREFH
5 Includes power-up of ADC and V
REF
6 ADC clock cycles
7 The current that can be injected or sourced from an unselected ADC signal input without impacting the performance of the
ADC
Table 35. ADC Parameters1 (continued)
Name
Characteristic
Min
Typical
Max
Unit
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