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参数资料
型号： MC8640VU1067NE
厂商： Freescale Semiconductor
文件页数： 112/130页
文件大小： 0K
描述： IC MPU SGL CORE E600 1023FCCBGA
标准包装： 1
系列： MPC86xx
处理器类型： 32-位 MPC86xx PowerPC
速度： 1.067GHz
电压： 0.95V
安装类型： 表面贴装
封装/外壳： 994-BCBGA，FCCBGA
供应商设备封装： 994-FCCBGA（33x33）
包装： 托盘
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3
82
Freescale Semiconductor
Serial RapidIO
components are included in this requirement. The reference impedance for return loss measurements is
100-
Ω resistive for differential return loss and 25-Ω resistive for common mode.
Table 59. Receiver AC Timing Specifications—1.25 GBaud
Parameter
Symbol
Range
Unit
Notes
Min
Max
Differential Input Voltage
VIN
200
1600
mV p-p
Measured at receiver
Deterministic Jitter Tolerance
JD
0.37
—
UI p-p
Measured at receiver
Combined Deterministic and Random
Jitter Tolerance
JDR
0.55
—
UI p-p
Measured at receiver
Total Jitter Tolerance1
JT
0.65
—
UI p-p
Measured at receiver
Multiple Input Skew
SMI
—
24
ns
Skew at the receiver input
between lanes of a multilane
link
Bit Error Rate
BER
—
10–12
——
Unit Interval
UI
800
ps
+/– 100 ppm
Note:
1. Total jitter is composed of three components, deterministic jitter, random jitter and single frequency sinusoidal jitter. The
sinusoidal jitter may have any amplitude and frequency in the unshaded region of Figure 55. The sinusoidal jitter component
is included to ensure margin for low frequency jitter, wander, noise, crosstalk and other variable system effects.
Table 60. Receiver AC Timing Specifications—2.5 GBaud
Parameter
Symbol
Range
Unit
Notes
Min
Max
Differential Input Voltage
VIN
200
1600
mV p-p
Measured at receiver
Deterministic Jitter Tolerance
JD
0.37
—
UI p-p
Measured at receiver
Combined Deterministic and Random
Jitter Tolerance
JDR
0.55
—
UI p-p
Measured at receiver
Total Jitter Tolerance1
JT
0.65
—
UI p-p
Measured at receiver
Multiple Input Skew
SMI
—
24
ns
Skew at the receiver input
between lanes of a multilane
link
Bit Error Rate
BER
—
10–12
——
Unit Interval
UI
400
ps
± 100 ppm
Note:
1. Total jitter is composed of three components, deterministic jitter, random jitter and single frequency sinusoidal jitter. The
sinusoidal jitter may have any amplitude and frequency in the unshaded region of Figure 55. The sinusoidal jitter component
is included to ensure margin for low frequency jitter, wander, noise, crosstalk and other variable system effects.
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