参数资料
型号: MAX8982EWO+T
厂商: Maxim Integrated Products
文件页数: 43/73页
文件大小: 0K
描述: IC PWR MGMT ICERA E400 42WLP
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,000
应用: 电源,ICERA E400,E450
输入电压: 4.1 V ~ 5.5 V
输出数: 13
输出电压: 可编程
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 42-WFBGA,WLCSP
供应商设备封装: 42-WLP
包装: 带卷 (TR)
MAX8982A/MAX8982P/MAX8982X
Power-Management ICs for
ICERA E400 Platform
4)
5)
6)
7)
8)
9)
The master sends the 8-bit register pointer of the first
register to write.
The slave acknowledges the register pointer.
The master sends a data byte.
The slave acknowledges the data byte.
The slave updates with the new data.
Steps 6 to 8 are repeated for as many registers in
the block, with the register pointer automatically
4)
5)
6)
7)
8)
9)
The master sends an 8-bit register pointer of the first
register in the block.
The slave acknowledges the register pointer.
The master sends a repeated START condition.
The master sends the 7-bit slave address followed
by a read bit.
The slave asserts an acknowledge by pulling SDA low.
The slave sends the 8-bit data (contents of the register).
incremented each time.
10) The master sends a STOP condition.
Read Operations
Use the following method to read a sequential block of
registers (Figure 18):
1) The master sends a start command.
2) The master sends the 7-bit slave address followed
by a write bit (0x83).
3) The addressed slave asserts an acknowledge by
pulling SDA low.
LEGEND
MASTER TO
SLAVE
SLAVE TO
MASTER
a) READING A SINGLE REGISTER
10) The master asserts an acknowledge by pulling
SDA low when there is more data to read, or a not
acknowledge by keeping SDA high when all data
has been read.
11) Steps 9 and 10 are repeated for as many registers
in the block, with the register pointer automatically
incremented each time.
12) The master sends a STOP condition.
The register pointer can be omitted from the above pro-
cedure when starting from register 0x00.
1
S
7
SLAVE ADDRESS
1
0
1
A
8
REGISTER POINTER
1 1
A Sr
7
SLAVE ADDRESS
1
1
1
A
8
DATA
1
A
1
P
NUMBER OF BITS
R/W
b) READING MULTIPLE REGISTERS
R/W
1
7
1
1
8
1
1
7
1 1
8
1
NUMBER OF BITS
S
SLAVE ADDRESS
0
A
REGISTER POINTER X
A
Sr
SLAVE ADDRESS
1
A
DATA X
A
...
R/W
R/W
8
1
8
1
8
1
1
NUMBER OF BITS
...
DATA X+1
A ...
DATA X+n-1
A
DATA X+n
A P
Figure 18. Reading from the ICs
Maxim Integrated
43
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