参数资料
| 型号： | LTC1703IG#TR |
| 厂商： | Linear Technology |
| 文件页数： | 11/36页 |
| 文件大小： | 0K |
| 描述： | IC CTLR REG SW DUAL 2PH 28-SSOP |
| 标准包装： | 2,000 |
| 应用： | 控制器，移动式 Intel Pentium? III |
| 输入电压： | 3 V ~ 7 V |
| 输出数： | 2 |
| 输出电压： | 0.9 V ~ 2 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-SSOP（0.209"，5.30mm 宽） |
| 供应商设备封装： | 28-SSOP |
| 包装： | 带卷 (TR) |
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LTC1703
APPLICATIO S I FOR ATIO
This constant frequency operation brings with it a couple
V IN
of benefits. Inductor and capacitor values can be chosen
with a precise operating frequency in mind and the feed-
PV CC
BOOST
D CP
+
C IN
back loop components can be similarly tightly specified.
Noise generated by the circuit will always be in a known
frequency band with the 550kHz frequency designed to
TG
SW
C CP
1 μ F
QT
L EXT
V OUT
leave the 455kHz IF band free of interference. Subharmonic
oscillation and slope compensation, common headaches
LTC1703
PGND
BG
QB
+
C OUT
with constant frequency current mode switchers, are
absent in voltage mode designs like the LTC1703.
During the time that QT is on, its source (the SW pin) is at
V IN . V IN is also the power supply for the LTC1703. How-
ever, QT requires V IN + V GS(ON) at its gate to achieve
minimum R ON . This presents a problem for the LTC1703—
it needs to generate a gate drive signal at TG higher than
its highest supply voltage. To accomplish this, the TG
driver runs from floating supplies, with its negative supply
attached to SW and its power supply at BOOST. This allows
it to slew up and down with the source of QT. In combination
with a simple external charge pump (Figure 2), this allows
the LTC1703 to completely enhance the gate of QT without
requiring an additional, higher supply voltage.
The two channels of the LTC1703 run from a common
clock, with the phasing chosen to be 180 ° from side 1 to
side 2. This has the effect of doubling the frequency of the
switching pulses seen by the input bypass capacitor,
significantly lowering the RMS current seen by the capaci-
tor and reducing the value required (see the 2-Phase
section).
Feedback Amplifier
Each side of the LTC1703 senses the output voltage at
V OUT with an internal feedback op amp (see Block Dia-
gram). This is a real op amp with a low impedance output,
85dB open-loop gain and 25MHz gain-bandwidth product.
1703 F02
Figure 2. Floating TG Driver Supply
topology with the FB pin configured as a virtual ground.
This allows flexibility in choosing pole and zero locations
not available with simple g m configurations. In particular,
it allows the use of “type 3” compensation, which pro-
vides a phase boost at the LC pole frequency and signifi-
cantly improves loop phase margin (see Figure 3). The
Feedback Loop/Compensation section contains a de-
tailed explanation of type 3 feedback loops. Note that side
1 of the LTC1703 includes R1 and R B internally as part
of the VID DAC circuitry.
MIN/MAX COMPARATORS
Two additional feedback loops keep an eye on the primary
feedback amplifier and step in if the feedback node moves
± 5% from its nominal 800mV value. The MAX comparator
(see Block Diagram) activates whenever FB rises more
than 5% above 800mV. It immediately turns the top
MOSFET (QT) off and the bottom MOSFET (QB) on and
keeps them that way until FB falls back within 5% of its
nominal value. This pulls the output down as fast as pos-
sible, preventing damage to the (often expensive) load. If
FB rises because the output is shorted to a higher supply,
QB will stay on until the short goes away, the higher supply
The positive input is connected internally to an 800mV
reference, while the negative input is connected to the FB
pin. The output is connected to COMP, which is in turn
COMP
FB
+
–
0.8V
FB
R3
R1
C3
V OUT
connected to the soft-start circuitry and from there to the
PWM generator.
C2
R B
Unlike many regulators that use a resistor divider con-
nected to a high impedance feedback input, the LTC1703
R2
C1
1703 F03
is designed to use an inverting summing amplifier
Figure 3. “Type 3” Feedback Loop (Side 2 Shown)
1703fa
11
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