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参数资料
| 型号： | LTC1400CS8 |
| 厂商： | Linear Technology |
| 文件页数： | 9/20页 |
| 文件大小： | 0K |
| 描述： | IC A/D CONV 12BIT W/SHTDN 8-SOIC |
| 标准包装： | 100 |
| 位数： | 12 |
| 采样率（每秒）： | 400k |
| 数据接口： | MICROWIRE?，串行，SPI? |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 160mW |
| 电压电源： | 双 ± |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 8-SOIC |
| 包装： | 管件 |
| 输入数目和类型： | 1 个单端，单极；1 个单端，双极 |
LTC1400
17
1400fa
THIS PROGRAM DEMONSTRATES LTC1400 INTERFACE TO ADSP-2181
FRAME SYNC PULSE IS GENERATED FROM RFS0
/*Section 1: Initialization*/
.module/ram/abs = 0 adspltc; /*dene the program module*/
jump start;
/*jump over interrupt vectors*/
nop; nop; nop;
rti; rti; rti; rti;
/*code vectors here upon IRQ2 int*/
rti; rti; rti; rti;
/*code vectors here upon IRQL1 int*/
rti; rti; rti; rti;
/*code vectors here upon IRQL0 int*/
rti; rti; rti; rti;
/*code vectors here upon SPORT0 TX int*/
ax0 = rx0;
/*Section 5*/
dm (0x2000) = ax0; /*begin of SPORT0 receive interrupt*/
rti;
/* */
/*end of SPORT0 receive interrupt*/
rti; rti; rti; rti;
/*code vectors here upon /IRQE int*/
rti; rti; rti; rti;
/*code vectors here upon BDMA interrupt*/
rti; rti; rti; rti;
/*code vectors here upon SPORT1 TX (IRQ1) int*/
rti; rti; rti; rti;
/*code vectors here upon SPORT1 RX (IRQ0) int*/
rti; rti; rti; rti;
/*code vectors here upon TIMER int*/
rti; rti; rti; rti;
/*code vectors here upon POWER DOWN int*/
/*Section 2: Congure SPORT0*/
start:
/*to congure SPORT0 control reg*/
/*SPORT0 address = 0X3FF6*/
/*RFS is used for frame sync generation*/
/*RFS0 is internal, TFS is not use*/
/*bit 0-3 = Slen*/
/*F = 15 = 1111*/
/*E = 14 = 1110*/
/*D = 13 = 1101*/
/*bit 4,5 data type right justied zero lled MSB*/
/*bit 6 INVRFS = 0*/
/*bit 7 INVTFS = 0*/
/*bit 8 IRFS = 1 receive internal frame sync*/
/*bit 9,10,11 are for TFS (don’t care)*/
/*bit 12 TFSW = 1 receive is Normal mode*/
/*bit 13 RTFS = 1 receive is framed mode*/
/*bit 14 ISCLK internal = 1*/
/*bit 15 multichannel mode = 0*/
ax0 = 0x6B0D;
/*normal mode, bit12 = 0*/
/*if alternate mode bit12 = 1, ax0 = 0x7F0E*/
dm (0x3FF6) =ax0;
/*Section 3: congure CLKDIV and RFSDIV, setup interrupts*/
/*to congure CLKDIV reg*/
ax0 = 2;
dm(0x3FF5) = ax0; /*set the serial clock divide modulus reg
SCLKDIV*/
/*the input clock frequency = 16.67MHz*/
/*CLKOUT frequency = 2x = 33MHz*/
/*SCLK= 1/2*CLKOUT*1/(SCLKDIV+1)*/
/*for SCLKDIV = 2, SCLK = 33/6 = 5.5MHz*/
/*to Congure RFSDIV*/
ax0 = 15;
/*set the RFSDIV reg = 15*/
/*= > the frame sync pulse for every 16 SCLK*/
/*if frame sync pulse in every 15 SCLK, ax0 = 14*/
dm(0x3FF4) = ax0;
/*to setup interrupt*/
ifc = 0x0066;
/*clear any extraneous SPORT interrupts*/
icntl = 0;
/*IRQXB = level sensitivity*/
/*disable nesting interrupt*/
imask= 0x0020;
/*bit 0 = timer int = 0*/
/*bit 1 = SPORT1 or IRQ0B int = 0*/
/*bit 2 = SPORT1 or IRQ1B int = 0*/
/*bit 3 = BDMA int = 0*/
/*bit 4 = IRQEB int = 0*/
/*bit 5 = SPORT0 receive int = 1*/
/*bit 6 = SPORT0 transmit int = 0*/
/*bit 7 = IRQ2B int = 0*/
/*enable SPORT0 receive interrupt*/
/*Section 4: Congure System Control Register and Start Communication*/
/*to congure system control reg*/
ax0 = dm(0x3FFF);
/*read the system control reg*/
ay0 = 0xFFF0;
ar = ax0 AND ay0;
/*set wait state to zero*/
ay0 = 0x1000;
ar = ar OR ay0;
/*bit12 = 1, enable SPORT0*/
dm(0x3FFF) = ar;
/*frame sync pulse regenerated automatically*/
cntr = 5000;
do waitloop until ce;
nop;
waitloop: nop;
rts;
.endmod;
TYPICAL APPLICATIO S
U
ADSP2181 Code for Circuit
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