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| 型号： | LT1186FCS#PBF |
| 厂商： | Linear Technology |
| 文件页数： | 3/16页 |
| 文件大小： | 0K |
| 描述： | IC SWTCH REG CCFL DAC PROG16SOIC |
| 标准包装： | 50 |
| 系列： | Bits-to-Nits™ |
| 类型： | CCFL 控制器 |
| 频率： | 175 ~ 225 kHz |
| 电流 - 电源： | 6mA |
| 电源电压： | 3 V ~ 6.5 V |
| 工作温度： | 0°C ~ 100°C |
| 封装/外壳： | 16-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 16-SOIC |
| 包装： | 管件 |
LT1186F
ELECTRICAL CHARACTERISTICS
T A = 25 ° C, V CC = SHUTDOWN = D IN = CS = 3.3V, BAT = Royer = BULB = 12V, I CCFL = CCFL V SW = Open, D OUT = Three-State, DIO = I OUT
= CLK = GND, CCFL V C = 0.5V, unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
CCFL High-Side Sense Servo Current
CCFL High-Side Sense Servo Current
Line Regulation
I CCFL = 100 μ A, I(V C ) = 0 μ A at CCFL V C = 1.5V
T J < 0 ° C
BAT = 5V to 30V, I CCFL = 100 μ A,
I(V C ) = 0 μ A at CCFL V C = 1.5V
q
q
0.93
0.91
1.00
1.00
0.1
1.07
1.07
0.16
A
A
%/V
CCFL High-Side Sense Supply Current Current Measured into BAT and Royer Pins
q
50
100
150
μ A
BULB Protect Servo Voltage
I CCFL = 100 μ A, I(V C ) = 0 μ A at CCFL V C = 1.5V,
q
6.5
7.0
7.5
V
Servo Voltage Measured between BAT and BULB Pins
BULB Input Bias Current
I CCFL = 100 μ A, I(V C ) = 0 μ A at CCFL V C = 1.5V
5
9
μ A
I LIM
V SAT
? I Q
? I SW
CCFL Switch Current Limit
CCFL Switch On Resistance
Supply Current Increase During
CCFL Switch On Time
Duty Cycle = 50%
Duty Cycle = 75% (Note 3)
CCFL I SW = 1A
CCFL I SW = 1A
q
q
q
1.25
0.9
1.9
1.6
0.6
20
3.0
2.6
1.0
30
A
A
?
mA/A
DAC Resolution
8
Bits
DAC Full-Scale Current
V(I OUT ) = 0.465V, Measured in SPI Mode
q
48.5
47.0
50
50
51.5
53.0
μ A
μ A
DAC Zero Scale Current
DAC Differential Nonlinearity
V(I OUT ) = 0.465V, Measured in SPI Mode
q
200
± 2.0
nA
LSB
DAC Supply Voltage Rejection
Logic Input Current
3V ≤ V CC ≤ 6.5V, I OUT = Full Scale, V(I OUT ) = 0.465V
0V ≤ V IN ≤ V CC
q
q
2
4
± 1
LSB
μ A
V IH
V IL
V OH
V OL
I OZ
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
Low Level Output Voltage
Three-State Output Leakage
V CC = 3.3V
V CC = 5V
V CC = 3.3V
V CC = 5V
V CC = 3.3V, I O = 400 μ A
V CC = 5V, I O = 400 μ A
V CC = 3.3V, I O = 1mA
V CC = 5V, I O = 2mA
V CS = V CC
q
q
q
q
q
q
q
q
q
1.9
2
2.1
2.4
0.45
0.80
0.4
0.4
± 5
V
V
V
V
V
V
V
V
μ A
SERIAL INTERFACE (Notes 4, 5)
f CLK
t CKS
t CSS
Clock Frequency
Setup Time, CLK ↓ Before CS ↓
Setup Time, CS ↓ Before CLK ↑
q
q
q
150
400
2
MHz
ns
ns
t DV
t DS
t DH
t DO
t CKHI
t CKLO
t CSH
t DZ
t CKH
CS ↓ to D OUT Valid
Data in Setup Time Before CLK ↑
Data in Hold Time After CLK ↑
CLK ↓ to D OUT Valid
CLK High Time
CLK Low Time
CLK ↓ Before CS ↑
CS ↑ to D OUT In Hi-Z
CS ↑ Before CLK ↑
See Test Circuits
See Test Circuits
See Test Circuits
q
q
q
q
q
q
q
q
q
150
150
150
150
200
250
150
400
400
ns
ns
ns
ns
ns
ns
ns
ns
ns
3
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