参数资料
型号: IDT70V09L15PF8
厂商: IDT, Integrated Device Technology Inc
文件页数: 7/17页
文件大小: 0K
描述: IC SRAM 1MBIT 15NS 100TQFP
标准包装: 750
格式 - 存储器: RAM
存储器类型: SRAM - 双端口,异步
存储容量: 1M (128K x 8)
速度: 15ns
接口: 并联
电源电压: 3 V ~ 3.6 V
工作温度: 0°C ~ 70°C
封装/外壳: 100-LQFP
供应商设备封装: 100-TQFP(14x14)
包装: 带卷 (TR)
其它名称: 70V09L15PF8
IDT70V09L
High-Speed 128K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range
70V09L15
Com'l Only
70V09L20
Com'l
& Ind
Symbol
Parameter
Min.
Max.
Min.
Max.
Unit
READ CYCLE
t RC
t AA
Read Cycle Time
Address Access Time
15
____
____
15
20
____
____
20
ns
ns
t ACE
Chip Enable Access Time
(3)
____
15
____
20
ns
t AOE
t OH
t LZ
t HZ
Output Enable Access Time
Output Hold from Address Change
Output Low-Z Time (1,2)
Output High-Z Time (1,2)
____
3
3
____
10
____
____
10
____
3
3
____
12
____
____
10
ns
ns
ns
ns
t PU
Chip Enab le to Power Up Time
(2)
0
____
0
____
ns
t PD
Chip Disable to Power Down Time
(2)
____
15
____
20
ns
t SOP
t SAA
Semaphore Flag Update Pulse ( OE or SEM )
Semaphore Address Access Time
10
____
____
15
10
____
____
20
ns
ns
4852 tbl 12
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage
70V09L15
Com'l Only
70V09L20
Com'l
& Ind
Symbol
Parameter
Min.
Max.
Min.
Max.
Unit
WRITE CYCLE
t WC
Write Cycle Time
15
____
20
____
ns
t EW
Chip Enable to End-of-Write
(3)
12
____
15
____
ns
t AW
Address Valid to End-of-Write
12
____
15
____
ns
t AS
Address Set-up Time
(3)
0
____
0
____
ns
t WP
t WR
t DW
t HZ
t DH
t WZ
Write Pulse Width
Write Recovery Time
Data Valid to End-of-Write
Output High-Z Time (1,2)
Data Hold Time (4)
Write Enable to Output in High-Z (1,2)
12
0
10
____
0
____
____
____
____
10
____
10
15
0
15
____
0
____
____
____
____
10
____
10
ns
ns
ns
ns
ns
ns
t OW
t SWRD
t SPS
Output Active from End-of-Write
SEM Flag Write to Read Time
SEM Flag Contention Window
(1,2,4)
0
5
5
____
____
____
0
5
5
____
____
____
ns
ns
ns
NOTES:
4852 tbl 13
1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2).
2. This parameter is guaranted by device characterization, but is not production tested.
3. To access RAM, CE = V IL and SEM = V IH . To access semaphore, CE = V IH and SEM = V IL . Either condition must be valid for the entire t EW time.
4. The specification for t DH must be met by the device supplying write data to the RAM under all operating conditions. Although t DH and t OW values will vary over voltage and
temperature, the actual t DH will always be smaller than the actual t OW .
7
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