参数资料
| 型号： | EL5126CL |
| 厂商： | Intersil |
| 文件页数： | 8/12页 |
| 文件大小： | 0K |
| 描述： | IC VOLTAGE GEN 8CH TFT-LCD 32QFN |
| 标准包装： | 60 |
| 应用： | 转换器，TFT，LCD |
| 输入电压： | 4.5 V ~ 16.5 V |
| 输出数： | 8 |
| 输出电压： | 0.5 V ~ 14.95 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-VFQFN 裸露焊盘 |
| 供应商设备封装： | 32-QFN 裸露焊盘（5x6） |
| 包装： | 散装 |
EL5126
I 2 C Timing Diagram 2
positive than the V COM potential. The second EL5126 can
provide the Gamma correction voltage more negative than
START
CONDITION
t R
t F
STOP CONDITION
the V COM potential. The Application Drawing shows a
system connected in this way.
CLOCK OSCILLATOR
DATA
CLOCK
The EL5126 requires an internal clock or external clock to
refresh its outputs. The outputs are refreshed at the falling OSC
clock edges. The output refreshed switches open at the rising
edges of the OSC clock. The driving load shouldn’t be changed
t S
t H
t S
t H
t R
t F
at the rising edges of the OSC clock. Otherwise, it will generate
a voltage error at the outputs. This clock may be input or output
V OUT ( IDEAL ) = V REFL + ------------- × ( V REFH - V REFL )
START, STOP & TIMING DETAILS OF I 2 C INTERFACE
Analog Section
TRANSFER FUNCTION
The transfer function is:
data
1024
where data is the decimal value of the 10-bit data binary
input code.
The output voltages from the EL5126 will be derived from
the reference voltages present at the V REFL and V REFH
pins. The impedance between those two pins is about 32k Ω .
Care should be taken that the system design holds these two
reference voltages within the limits of the power rails of the
EL5126. GND < V REFH ≤ V S and GND ≤ V REFL ≤ V REFH .
In some LCD applications that require more than 8 channels,
the system can be designed such that one EL5126 will
provide the Gamma correction voltages that are more
8
via the clock pin labeled OSC. The internal clock is provided by
an internal oscillator running at approximately 21kHz and can
be output to the OSC pin. In a 2 chip system, if the driving loads
are stable, one chip may be programmed to use the internal
oscillator; then the OSC pin will output the clock from the
internal oscillator. The second chip may have the OSC pin
connected to this clock source.
For transient load application, the external clock Mode
should be used to ensure all functions are synchronized
together. The positive edge of the external clock to the OSC
pin should be timed to avoid the transient load effect. The
Application Drawing shows the LCD H rate signal used, here
the positive clock edge is timed to avoid the transient load of
the column driver circuits.
After power on, the chip will start with the internal oscillator
mode. At this time, the OSC pin will be in a high impedance
condition to prevent contention. By setting pin 32 to high, the
chip is on external clock mode. Setting pin 32 to low, the chip
is on internal clock mode.
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