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| 型号： | CPC5903G |
| 厂商： | IXYS Integrated Circuits Division |
| 文件页数： | 10/15页 |
| 文件大小： | 0K |
| 描述： | ISOL 3.75KVRMS 1CH BIDIR 8-DIP |
| 标准包装： | 50 |
| 电压 - 隔离： | 3750Vrms |
| 通道数： | 1，双向 |
| 数据速率： | 400kbps |
| 输入类型： | DC |
| 输出类型： | I²C? |
| 安装类型： | 通孔 |
| 封装/外壳： | 8-DIP（0.300"，7.62mm） |
| 供应商设备封装： | 8-DIP |
| 包装： | 管件 |
I NTEGRATED C IRCUITS D IVISION
Thus normal-width pulses of width t PULSE applied at
IOB exhibit a stretched pulse width of:
t PWB_nom = t PULSE + t FIL + t OPLH_BA + t SLEWA + t OPLH_AB
at IOB, which is also given by:
t PWB_nom = t PULSE + t PHL_BAB
and is typically t PULSE + 290ns.
Side A receivers have been designed to exhibit a
significant amount of hysteresis, which helps to
eliminate false clocking. They have not been internally
low-pass filtered beyond the filtering inherent within
the optical channel. When the I 2 C bus is terminated
for maximum bandwidth (6mA pullups and minimal
capacitance), the receivers typically will respond to
pulses greater than 12ns. If additional filtering is
desired, then externally increasing the load
capacitance of the I 2 C lines, until the amount of time
the offending signal spends above/below V DD /2 is
less than 10ns, will reject the signal at the expense of
increasing rise and fall times.
The Side B receiver does implement some hysteresis
and low-pass filtering in addition to the optics. An
asserted pulse typically needs to be held below
0.2V DD for 15ns before it is accepted at the Side B
input. This may require a 30ns pulse applied by a
typical driver with just 20pF loading the I 2 C lines.
While any very short pulse stretched to the minimum
time above would seem to cause a large amount of
pulse width distortion, within 400kHz Fast-mode I 2 C,
the shortest allowable signal or clock asserted low
time is 1.3 ? s. Neither Standard-mode nor Fast-mode
variants include any legal signals that are less than
80ns (typ); thus the t PWA_nom and t PWB_nom equations
above always apply. The pulse width on valid longer
pulses receives less stretching and is proportionally
less noticeable. For example the Fast-mode minimum
clock low time of 1.3 ? S when applied at Side B would
typically be seen as a 1.375 ? S pulse at Side A and will
be stretched to a length of 1.59 ? s for other devices on
the Side B bus.
Internal filtering and the flip-flop at IOB are used to
ensure that an equal number of pulse edges are seen
at both sides of the isolation barrier when Side B is
driven. When a signal at IOB is asserted low, the
flip-flop self-drives the IOB pin until the optical channel
back from Side A proves that Side A has successfully
been asserted. While this is generally a welcome error
CPC5903
reduction feature and is especially useful on the side
with nonstandard levels, it does need to be considered
when assigning Side A and Side B ports. If Side A is
not powered up, then the signal back from Side A will
not appear until after Side A has been powered, and
the signal at Side B will be stretched until that time.
Side A uses filtered hysteresis at its standard inputs,
not pulse stretching, to defeat sub-minimum-size
pulses. Thus that side of the isolation barrier, which
will be the bus master at power-up, should be
assigned to Side A.
3.6 Start-Up
Upon startup and with loss of V DDx , internal circuitry
place the outputs in the deasserted Hi-Z state.
3.7 Power Supply Decoupling and Noise
There are no special power supply decoupling
requirements for the CPC5903. Additionally, because
the CPC5903 uses optical coupling to transfer clock
and data across the barrier there are no internal
clocking circuits requiring special layout or noise
reduction techniques to maintain EMI and RFI
compliance.
10
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