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| 型号： | BD10KA5WF-E2 |
| 厂商： | Rohm Semiconductor |
| 文件页数： | 12/18页 |
| 文件大小： | 0K |
| 描述： | IC REG LDO 1V .5A SOP8 |
| 特色产品： | CMOS LDO Regulators |
| 标准包装： | 1 |
| 稳压器拓扑结构： | 正，固定式 |
| 输出电压： | 1V |
| 输入电压： | 2.3 V ~ 5.5 V |
| 稳压器数量： | 1 |
| 电流 - 输出： | 500mA（最小值） |
| 工作温度： | -40°C ~ 105°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-SOIC（0.173"，4.40mm 宽） |
| 供应商设备封装： | 8-SOP |
| 包装： | 标准包装 |
| 产品目录页面： | 1370 (CN2011-ZH PDF) |
| 其它名称： | BD10KA5WF-E2DKR |
BDxxKA5 Series BDxxKA5W Series
BD00KA5W Series
Datasheet
● Operational Notes
○ Protection Circuits
Over-current Protection Circuit
A built-in over-current protection circuit corresponding to the current capacity prevents the destruction of the IC when
there are load shorts. This protection circuit is a “7”-shaped current control circuit that is designed such that the current is
restricted and does not latch even when a large current momentarily flows through the system with a high-capacitance
capacitor. However, while this protection circuit is effective for the prevention of destruction due to unexpected accidents,
it is not suitable for continuous operation or transient use. Please be aware when creating thermal designs that the
over-current protection circuit has negative current capacity characteristics with regard to temperature.
○ Thermal Shutdown Circuit (Thermal Protection)
This system has a built-in temperature protection circuit for the purpose of protecting the IC from thermal damage. As
shown in Fig. 20-22, this must be used within the range of acceptable loss, but if the acceptable loss is continuously
exceeded, the chip temperature Tj increases, causing the thermal shutdown circuit to operate. When the thermal shutdown
circuit operates, the operation of the circuit is suspended. The circuit resumes operation immediately after the chip
temperature Tj decreases, so the output repeats the ON and OFF states (Please refer to Fig.17 for the temperatures at
which the temperature protection circuit operates).
There are cases in which the IC is destroyed due to thermal runaway when it is left in the overloaded state. Be sure to
avoid leaving the IC in the overloaded state.
○ Reverse Current
In order to prevent the destruction of the IC when a reverse current flows through the IC, it is recommended that a diode
be placed between the Vcc and Vo and a pathway be created so that the current can escape (Refer to Fig.27).
Reverse current
Vcc
CTL
GND
OUT
Fig.27 Bypass diode
○ This IC is BI-CMOS IC that has a P-board (substrate) and P+ isolation between each element, as shown in Fig.28. A P-N
junction is formed between this P-layer and the N-layer of each element, and the P-N junction operates as :
- a parasitic diode when the electric potential relationship is GND> Pin A, GND> Pin B, or
- a parasitic transistor when the electric potential relationship is Pin B > GND> Pin A.
Parasitic elements are structurally inevitable in the IC. The operation of parasitic elements induces mutual interference
between circuits, causing malfunctions and eventually the destruction of the IC. Take precaution as not to use the IC in
ways that would cause parasitic elements to operate. For example, applying a voltage that is lower than the GND (P-board)
to the input terminal.
Transistor (NPN)
Resistor
(Pin B) C
B
E
(Pin A)
(Pin B)
GND
B
C
E
P
P+
N
Parasitic element
or transistor
N
N
P
P
GND
P+
N
N
P
P+
N
P+
N
Parasitic element
GND
(Pin A)
GND
Parasitic element
or transistor
Parasitic element
GND
Fig.28 Basic structure example
Status of this document
The Japanese version of this document is formal specification. A customer may use this translation version only for a reference to
help reading the formal version.
If there are any differences in translation version of this document formal version takes priority.
www.rohm.com
? 2012 ROHM Co., Ltd. All rights reserved.
TSZ22111 ? 15 ? 001
12/15
TSZ02201-0R6R0A600150-1-2
26.Jun.2012 Rev.001
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