参数资料
型号: A3992SB-T
厂商: Allegro Microsystems Inc
文件页数: 5/13页
文件大小: 0K
描述: IC MOTOR DRVR PWM DUAL 24-DIP
标准包装: 4,500
应用: PWM 电机驱动器,步进电机驱动器
输出数: 1
电流 - 输出: ±1.5A
电压 - 负载: 15 V ~ 50 V
电源电压: 4.5 V ~ 5.5 V
工作温度: -20°C ~ 85°C
安装类型: 通孔
封装/外壳: 24-DIP(0.300",7.62mm)
供应商设备封装: 24-DIP
包装: 管件
其它名称: 620-1169-5
A3992
DMOS Dual Full-Bridge
Microstepping PWM Motor Driver
Serial Interface Description
The A3992 is controlled via a 3 wire serial port. The
programmable functions allow maximum ? exibility in
con ? guring the PWM to the motor drive requirements.
The serial data is written as two 19 bit words, 1 bit
to select which word (referred to here as Word 0 and
Word 1 ) and 18 bits of data. The serial port is de ? ned
D7 – 12 Bridge 2 Linear DAC. 6 bit word to set the
desired current level for bridge 2. Setting all bits to
zero disables Full Bridge 2, all drivers off. (See Cur-
rent Regulation in the Functional Description section.)
D13 Bridge 1 Phase. This bit controls the direction
of current for motor phase 1 as de ? ned below:
in the following tables and text descriptions.
Word 0 Bit Assignments
D13
0
1
OUT1A
L
H
OUT1B
H
L
Word 0 is selected by setting D0 = 0. Assignments are
summarized in the following table, and described in
detail in the remainder of this section.
D14 Bridge 2 Phase. This bit controls the direction
of current for motor phase 2 as de ? ned below:
Word 0 Bit Assignments
D14
OUT2A
OUT2B
Bit
D0
Function
Word Select = 0
0
1
L
H
H
L
D1
D2
D3
Bridge 1, DAC, LSB
Bridge 1, DAC, Bit2
Bridge 1, DAC, Bit3
D15 Bridge 1 Mode. This bit determines the decay
for Full Bridge 1 as de ? ned below:
D4
D5
D6
Bridge 1, DAC, Bit4
Bridge 1, DAC, Bit 5
Bridge 1, DAC, MSB
D15
0
1
Mode
Mixed Decay
Slow Decay
D7
D8
D9
Bridge 2, DAC, LSB
Bridge 2, DAC, Bit2
Bridge 2, DAC, Bit3
D16 Bridge 2 Mode. This bit determines the decay
for Full Bridge 2 as de ? ned below:
D10
D11
D12
Bridge 2, DAC, Bit4
Bridge 2, DAC, Bit 5
Bridge 2, DAC, MSB
D16
0
1
Mode
Mixed Decay
Slow Decay
D13
D14
D15
D16
D17
D18
Bridge 1 Phase
Bridge 2 Phase
Bridge 1 Mode
Bridge 2 Mode
Reference Select
Range Select
D17 Ref Select. This bit determines the reference
input for the two 6 bit linear DACs. Logic low selects
internal 2 V reference voltage, logic high selects ex-
ternal reference input on the REF pin.
D18 G m Range Select. D18 determines if the scaling
D1 – D6 Bridge 1, Linear DAC. 6 bit word to set de-
factor used is 4 or 8:
sired current level for bridge 1. Setting all bits to zero
disables Full Bridge 1, all drivers off. (See Current
Regulation in the Functional Description section.)
D18
0
1
Divider
÷8
÷4
Load Current
I TRIP = V DAC /( R SENSE × 8)
I TRIP = V DAC /( R SENSE × 4)
Allegro MicroSystems, LLC
115 Northeast Cutoff, Box 15036
5
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
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