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参数资料
| 型号： | 9704-11 |
| 厂商： | PEREGRINE SEMICONDUCTOR CORP |
| 元件分类： | PLL合成/DDS/VCOs |
| 英文描述： | 3.0 GHz Integer-N PLL for Rad Hard Apllications |
| 中文描述： | PHASE LOCKED LOOP, CQCC44 |
| 封装： | CERAMIC, QFJ-44 |
| 文件页数： | 4/10页 |
| 文件大小： | 247K |
| 代理商： | 9704-11 |
Product Specification
PE9704
Page 3 of 10
Document No. 70-0083-03
│ www.psemi.com
2003-2006 Peregrine Semiconductor Corp. All rights reserved.
Table 1. Pin Descriptions (continued)
17
GND
Both
Ground
18
CLOCK
Serial
Input
Clock input. Data is clocked serially into either the 20-bit primary register (E_WR
“low”) or the 8-bit enhancement register (E_WR “high”) on the rising edge of
CLOCK.
M6
Direct
Input
M Counter bit6
19
M7
Direct
Input
M Counter bit7
20
M8
Direct
Input
M Counter bit8 (MSB)
21
A0
Direct
Input
A Counter bit0
22
DMODE
Both
Input
Selects direct interface mode (DMODE=1) or serial interface mode (DMODE=0)
23
VDD
Both
(Note 1)
Same as pin 1
24
E_WR
Serial
Input
Enhancement register write enable. While E_WR is “high”, DATA can be serially
clocked into the enhancement register on the rising edge of CLOCK.
A1
Direct
Input
A Counter bit1.
25
A2
Direct
Input
A Counter bit2
26
A3
Direct
Input
A Counter bit3 (MSB)
27
FIN
Both
Input
RF prescaler input from the VCO. 3.0 GHz maximum frequency.
28
GND
Both
Ground.
29
GND
Both
Ground.
30
N/C
No connect.
31
VDD
Both
(Note 1)
Same as pin 1
32
DOUT
Serial
Output
Data Out. The Main Counter output, R Counter output, or dual modulus prescaler
select (MSEL) can be routed to DOUT through enhancement register programming.
33
VDD
Both
(Note 1)
Same as pin 1
34
N/C
No connect.
35
GND
Both
Ground.
36
PD_
D
Both
Output
PD_
D pulses down when f
p leads fc.
37
PD_
U
Both
PD_
U pulses down when f
c leads fp.
38
VDD
Both
(Note 1)
Same as pin 1
39
CEXT
Both
Output
Logical “NAND” of PD_
U and PD_D, passed through an on-chip, 2 k series
resistor. Connecting CEXT to an external capacitor will low pass filter the input to the
inverting amplifier used for driving LD.
40
GND
Both
Ground
41
GND
Both
Ground
42
FR
Both
Input
Reference frequency input
43
ENH
Both
Output, OD
Enhancement mode. When asserted low (“0”), enhancement register bits are
functional.
44
LD
Serial
Output
Lock detect output, the open-drain logical inversion of CEXT. When the loop is
locked, LD is high impedance; otherwise LD is a logic low (“0”).
Note 1:
VDD pins 1, 11, 12, 23, 31, 33, 35, and 38 are connected by diodes and must be supplied with the same positive voltage level.
Note 2:
All digital input pins have 70 k
pull-down resistors to ground.
Pin No.
Pin Name
Interface Mode
Type
Description
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相关代理商/技术参数 |
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| 97042002 | 制造商:Laird Technologies Inc 功能描述:CSTR FRG BF |
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| 970420361 | 功能描述:Hex Spacer Threaded M3x0.5 Steel 1.654" (42.00mm) 制造商:wurth electronics inc 系列:WA-SSTII 零件状态:新产品 类型:六角衬垫 有丝/无丝:有螺纹 公母:母头，母头 螺钉，螺纹规格:M3x0.5 直径 - 内部:- 直径 - 外部:0.236"（6.00mm） 六角形 板间高度:1.654"（42.00mm） 长度 - 总:1.654"（42.00mm） 特性:表面贴装型 材料:钢 镀层:锌 颜色:- 重量:- 标准包装:750 |
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