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参数资料
| 型号： | 951412AGLF |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 220 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56 |
| 封装： | 6.10 MM, 0.50 MM PITCH, GREEN, MO-153, TSSOP-56 |
| 文件页数： | 2/25页 |
| 文件大小： | 246K |
| 代理商： | 951412AGLF |
10
ICS951412
0883L—04/26/06
SMBus Table: Device ID Register
Pin #
Name
Control Function
Type0
1
PWD
Bit 7
DevID 7
Device ID MSB
R
-
0
Bit 6
DevID 6
Device ID 6
R
-
0
Bit 5
DevID 5
Device ID 5
R
-
0
Bit 4
DevID 4
Device ID4
R
-
1
Bit 3
DevID 3
Device ID3
R
-
0
Bit 2
DevID 2
Device ID2
R
-
0
Bit 1
DevID 1
Device ID1
R
-
1
Bit 0
DevID 0
Device ID LSB
R
-
0
SMBus Table: Vendor ID Register
Pin #
Name
Control Function
Type0
1
PWD
Bit 7
RID3
R
-
X
Bit 6
RID2
R
-
X
Bit 5
RID1
R
-
X
Bit 4
RID0
R
-
X
Bit 3
VID3
R
-
0
Bit 2
VID2
R
-
0
Bit 1
VID1
R
-
0
Bit 0
VID0
R
-
1
SMBus Table: Byte Count Register
Pin #
Name
Control Function
Type0
1
PWD
Bit 7
BC7
RW
0
Bit 6
BC6
RW
0
Bit 5
BC5
RW
0
Bit 4
BC4
RW
0
Bit 3
BC3
RW
1
Bit 2
BC2
RW
0
Bit 1
BC1
RW
0
Bit 0
BC0
RW
1
Bytes 9 to 21 are reserved
Byte 6
-
Writing to this register will
configure how many bytes
will be read back, default is 9
bytes.
-
Revision ID
-
VENDOR ID
(0001 = ICS)
-
Byte Count Programming
b(7:0)
-
Byte 8
-
Byte 7
-
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相关代理商/技术参数 |
参数描述 |
|---|---|
| 951412AGLFT | 制造商:Integrated Device Technology Inc 功能描述:PLL Clock Synthesizer Dual 56-Pin TSSOP T/R |
| 951412BFLF | 制造商:Integrated Device Technology Inc 功能描述:PLL Clock Synthesizer Dual 56-Pin SSOP Tube |
| 951412BFLFT | 制造商:Integrated Device Technology Inc 功能描述:PLL Clock Synthesizer Dual 56-Pin SSOP T/R |
| 951412BGLF | 功能描述:时钟合成器/抖动清除器 RoHS:否 制造商:Skyworks Solutions, Inc. 输出端数量: 输出电平: 最大输出频率: 输入电平: 最大输入频率:6.1 GHz 电源电压-最大:3.3 V 电源电压-最小:2.7 V 封装 / 箱体:TSSOP-28 封装:Reel |
| 951412BGLFT | 功能描述:时钟合成器/抖动清除器 RoHS:否 制造商:Skyworks Solutions, Inc. 输出端数量: 输出电平: 最大输出频率: 输入电平: 最大输入频率:6.1 GHz 电源电压-最大:3.3 V 电源电压-最小:2.7 V 封装 / 箱体:TSSOP-28 封装:Reel |
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