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参数资料
| 型号： | 950810CGLFT |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 200 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56 |
| 封装： | 6.10 MM, 0.50 MM PITCH, MO-153, TSSOP-56 |
| 文件页数： | 1/21页 |
| 文件大小： | 194K |
| 代理商： | 950810CGLFT |
Integrated
Circuit
Systems, Inc.
ICS950810
0472E—07/03/02
Block Diagram
Recommended Application:
CK-408 clock for BANIAS processor/ ODEM and
MONTARA-G chipsets.
Output Features:
3 Differential CPU Clock Pairs @ 3.3V
7 PCI (3.3V) @ 33.3MHz
3 PCI_F (3.3V) @ 33.3MHz
1 USB (3.3V) @ 48MHz
1 DOT (3.3V) @ 48MHz
1 REF (3.3V) @ 14.318MHz
5 3V66 (3.3V) @ 66.6MHz
1 VCH/3V66 (3.3V) @ 48MHz or 66.6MHz
Features:
Supports spread spectrum modulation,
down spread 0 to -0.5%. (CPU, 3V66, PCI)
Efficient power management scheme through PD#,
CPU_STOP# and PCI_STOP#.
Key Specifications:
CPU Output Jitter <150ps
3V66 Output Jitter <250ps
CPU Output Skew <100ps
Pin Configuration
56-Pin 300mil SSOP
6.10 mm. Body, 0.50 mm. pitch TSSOP
Frequency Generator with 200MHz Differential CPU Clocks
Functionality
* These inputs have 150K internal pull-up resistor to VDD.
2
S
F1
S
F0
S
F
U
P
C
)
z
H
M
(
)
0
:
5
(
6
V
3
)
z
H
M
(
F
_
I
C
P
I
C
P
)
z
H
M
(
X0
0
6
.
6
16
6
.
6
63
3
.
3
X0
1
0
.
0
16
6
.
6
63
3
.
3
X1
0
.
0
26
6
.
6
63
3
.
3
X1
1
3
.
3
16
6
.
6
63
3
.
3
d
i
M0
0
e
t
a
t
s
i
r
Te
t
a
t
s
i
r
Te
t
a
t
s
i
r
T
d
i
M0
1
2
/
K
L
C
T4
/
K
L
C
T8
/
K
L
C
T
d
i
M1
0
d
e
v
r
e
s
e
Rd
e
v
r
e
s
e
Rd
e
v
r
e
s
e
R
d
i
M1
1
d
e
v
r
e
s
e
Rd
e
v
r
e
s
e
Rd
e
v
r
e
s
e
R
VDDREF
1
56 REF
X1
2
55 FS1
X2
3
54 FS0
GND
4
53 CPU_STOP#*
PCICLK_F0
5
52 CPUCLKT0
PCICLK_F1
6
51 CPUCLKC0
PCICLK_F2
7
50 VDDCPU
VDDPCI
8
49 CPUCLKT1
GND
9
48 CPUCLKC1
PCICLK0 10
47 GND
PCICLK1 11
46 VDDCPU
PCICLK2 12
45 CPUCLKT2
PCICLK3 13
44 CPUCLKC2
VDDPCI 14
43 MULTSEL0*
GND 15
42 IREF
PCICLK4 16
41 GND
PCICLK5 17
40 FS2
PCICLK6 18
39 48MHz_USB
VDD3V66 19
38 48MHz_DOT
GND 20
37 VDD48
3V66_2 21
36 GND
3V66_3 22
35 3V66_1/VCH_CLK
3V66_4 23
34 PCI_STOP#*
3V66_5 24
33 3V66_0
*PD# 25
32 VDD3V66
VDDA 26
31 GND
GND 27
30 SCLK
Vtt_PWRGD# 28
29 SDATA
ICS
950810
PLL2
PLL1
Spread
Spectrum
3V66_5
3V66_3
3V66_(4,2)
48MHz_USB
48MHz_DOT
X1
X2
XTAL
OSC
3V66
DIVDER
PD#
CPU_STOP#
PCI_STOP#
MULTSEL0
SDATA
SCLK
FS (2:0)
I REF
Control
Logic
Config.
Reg.
REF
3V66_0
CPU
DIVDER
3
CPUCLKT (2:0)
CPUCLKC (2:0)
Stop
3V66_1/VCH_CLK
PCICLK (6:0)
PCI
DIVDER
3
7
PCICLK_F (2:0)
Stop
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