参数资料
型号: 950602CFT
厂商: INTEGRATED DEVICE TECHNOLOGY INC
元件分类: 时钟产生/分配
英文描述: 200 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48
封装: 0.300 INCH, MO-118, SSOP-48
文件页数: 1/18页
文件大小: 233K
代理商: 950602CFT
Integrated
Circuit
Systems, Inc.
ICS950602
0469B—12/18/02
Block Diagram
Pin Configuration
Recommended Application:
VIA Mobile PL133T and PLE133T Chipsets.
Output Features:
2 - CPU clocks @ 2.5V
1 - Pairs of differential CPU clocks @ 3.3V
7 - PCI including 1 free running @ 3.3V
7 - SDRAM @ 3.3V
1 - 48MHz @ 3.3V fixed
1 - 24_48MHz selectable @ 3.3V
2 - REF @ 3.3V, 14.318MHz
Features/Benefits:
Programmable output frequency.
Programmable output divider ratios.
Programmable output rise/fall time.
Programmable output skew.
Programmable spread percentage for EMI control.
Watchdog timer technology to reset system
if system malfunctions.
Programmable watch dog safe frequency.
Support I
2C Index read/write and block read/write
operations.
Uses external 14.318MHz crystal.
Key Specifications:
CPU Output Jitter <200ps
CPU Output Skew <175ps
PCI to PCI Output Skew <500ps
Programmable Timing Control Hub for PII/III
* Internal Pull-up resistor of 120K to VDD
** these inputs have 120K internal pull-down
to GND
48-Pin SSOP & TSSOP
GND
*FS2/REF1
REF0
Vtt_PWRGD#
VDDREF
GND
X1
X2
VDDPCI
*FS4/PCICLK_F
*FS3/PCICLK0
GND
PCICLK1
PCICLK2
PCICLK3
PCICLK4
PCICLK5
SDRAM_IN
*CPU_STOP#
*PCI_STOP#
*PD#
**MULTISEL
GND
SDATA
CPUCLK0
CPUCLK1
VDDCPU_2.5
VDDCPU_3.3
CPUCLKT
CPUCLKC
GND
RESET#
I REF
SDRAM6
GND
SDRAM0
SDRAM1
VDDSDRAM
SDRAM2
SDRAM3
GND
SDRAM4
SDRAM5
VDDSDRAM
AVDD48
48MHz/FS0*
24_48MHz/FS1*
SCLK
ICS950602
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相关PDF资料
PDF描述
950602CFLFT 200 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48
950602CG 200 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48
950602CF 200 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48
950602CGLFT 200 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48
950602CFLF 200 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48
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