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参数资料
| 型号： | 950405AFLFT |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 300 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封装： | 0.300 INCH, GREEN, MO-118, SSOP-48 |
| 文件页数： | 15/18页 |
| 文件大小： | 219K |
| 代理商： | 950405AFLFT |
6
ICS950405
0802F—04/22/05
I
2C Table: Frequency Select Register
Bit 7
SS_EN
Spread Enable
RW
1
Bit 6
SEL24_48MHz
Output Select
RW
Latch
Bit 5
Reserved
RW
X
Bit 4
Reserved
RW
X
Bit 3
FS3
Freq Select Bit 3
RW
Latch
Bit 2
FS2
Freq Select Bit 2
RW
Latch
Bit 1
FS1
Freq Select Bit 1
RW
Latch
Bit 0
FS0
Freq Select Bit 0
RW
Latch
I
2C Table: Output Control Register
Bit 7
REF0
Output Control
RW
1
Bit 6
HTTCLK0
Output Control
RW
1
Bit 5
PCICLK8/HTTCLK1
Output Control
RW
1
Bit 4
PCICLK9/HTTCLK2
Output Control
RW
1
Bit 3
PCICLK11/HTTCLK3
Output Control
RW
1
Bit 2
PCICLK10
Output Control
RW
1
Bit 1
PCICLK0
Output Control
RW
1
Bit 0
PCICLK1
Output Control
RW
1
I
2C Table: Output Control Register
Bit 7
PCICLK2
Output Control
RW
1
Bit 6
PCICLK3
Output Control
RW
1
Bit 5
PCICLK4
Output Control
RW
1
Bit 4
PCICLK5
Output Control
RW
1
Bit 3
PCICLK6
Output Control
RW
1
Bit 2
PCICLK7
Output Control
RW
1
Bit 1
24_48MHz
Output Control
RW
1
Bit 0
48MHz
Output Control
RW
1
I
2C Table: Output Control Register
Bit 7
CPUCLK8T/C_1
Output Control
RW
1
Bit 6
CPUCLK8T/C_0
Output Control
RW
1
Bit 5
REF2
Output Control
RW
1
Bit 4
REF1
Output Control
RW
1
Bit 3
PCI_Str1
RW
0
Bit 2
PCI_Str0
RW
1
Bit 1
PCI_Str1
RW
0
Bit 0
PCI_Str0
RW
1
PCI9,8 Strength
Control only
PCI11 Strength Control
only
-
00: 0.5X Drive
10: 1.5X Drive
-
01: 1.0X Drive
11: 2.0X Drive
-
00: 0.5X Drive
10: 1.5X Drive
-
01: 1.0X Drive
11: 2.0X Drive
45
Disable
Enable
48
Disable
Enable
37,36
Disable
Enable
41,40
Disable
Enable
Type
0
1
PWD
Byte 3
Pin #
Name
Control Function
28
Disable
Enable
31
Disable
Enable
23
Disable
Enable
24
Disable
Enable
21
Disable
Enable
22
Disable
Enable
17
Disable
Enable
18
Disable
Enable
Type
0
1
PWD
Byte 2
Pin #
Name
Control Function
13
Disable
Enable
14
Disable
Enable
11
Disable
Enable
12
Disable
Enable
7
Disable
Enable
8
Disable
Enable
1
Disable
Enable
6
Disable
Enable
Type
0
1
PWD
Byte 1
Pin #
Name
Control Function
-
Reserved
-
Reserved
See Table1: Frequency Selection Table
-
Type
0
1
-
OFF
ON
-
48MHz
24MHz
PWD
Byte 0
Pin #
Name
Control Function
相关PDF资料 |
PDF描述 |
|---|---|
| 950405AFLF | 300 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 950515 | 20 A, MODULAR TERMINAL BLOCK, 1 ROW, 1 DECK |
| 950513 | 20 A, MODULAR TERMINAL BLOCK, 1 ROW, 1 DECK |
| 950511 | 20 A, MODULAR TERMINAL BLOCK, 1 ROW, 1 DECK |
| 950510 | 20 A, MODULAR TERMINAL BLOCK, 1 ROW, 1 DECK |
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