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参数资料
| 型号： | 83336-21 |
| 厂商： | PEREGRINE SEMICONDUCTOR CORP |
| 元件分类： | PLL合成/DDS/VCOs |
| 英文描述： | 3.0 GHz Integer-N PLL for Low Phase Noise Applications |
| 中文描述： | PHASE LOCKED LOOP, CQCC44 |
| 封装： | CERAMIC, QFJ-44 |
| 文件页数： | 8/13页 |
| 文件大小： | 318K |
| 代理商： | 83336-21 |
Product Specification
PE83336
Page 4 of 13
2003-2006 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0137-02
│ UltraCMOS RFIC Solutions
Table 1. Pin Descriptions (continued)
Note 1:
All VDD pins are connected by diodes and must be supplied with the same positive voltage level.
VDD-fp and VDD-fp are used to power the fp and fc outputs and can alternatively be left floating or connected to GND to disable the fp and fc
outputs.
Note 2:
All digital input pins have 70 k
Ω pull-down resistors to ground.
30
fp
ALL
Output
Monitor pin for main divider output. Switching activity can be disabled through enhancement
register programming or by floating or grounding VDD pin 31.
31
VDD-fp
ALL
(Note 1)
VDD for fp. Can be left floating or connected to GND to disable the fp output.
32
Dout
Serial,
Parallel
Output
Data Out. The MSEL signal and the raw prescaler output are available on Dout through
enhancement register programming.
33
VDD
ALL
(Note 1)
Same as pin 1.
34
Cext
ALL
Output
Logical “NAND” of PD_
U and PD_D terminated through an on chip, 2 k
Ω series resistor.
Connecting Cext to an external capacitor will low pass filter the input to the inverting amplifier
used for driving LD.
35
VDD
ALL
(Note 1)
Same as pin 1.
36
PD_
D
ALL
Output
PD_
D is pulse down when f
p leads fc.
37
PD_
U
ALL
PD_
U is pulse down when f
c leads fp.
38
VDD-fc
ALL
(Note 1)
VDD for fc can be left floating or connected to GND to disable the fc output.
39
fc
ALL
Output
Monitor pin for reference divider output. Switching activity can be disabled through
enhancement register programming or by floating or grounding VDD pin 38.
40
GND
ALL
Ground.
41
GND
ALL
Ground.
42
fr
ALL
Input
Reference frequency input.
43
LD
ALL
Output
Lock detect and open drain logical inversion of CEXT. When the loop is in lock, LD is high
impedance, otherwise LD is a logic low (“0”).
44
Enh
Serial,
Parallel
Input
Enhancement mode. When asserted low (“0”), enhancement register bits are functional.
N/A
NC
ALL
No connection.
Pin No.
(44-lead
CQFJ)
Pin
Name
Interface
Mode
Type
Description
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