参数资料
型号: 73M2901CE-EVM-WW
厂商: Maxim Integrated Products
文件页数: 7/30页
文件大小: 0K
描述: BOARD DEMO 73M2901CE WORLDWIDE
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 1
系列: *

UM_2901CE_026
73M2901CE Demo Board User Manual
2 Design Considerations
Keep OSCIN and OSCOUT signals as short as possible and locate the crystal near the pins. Use an
11.0592 MHz parallel mode crystal only. Do not use ground planes under the oscillator circuit since this
will increase the parasitic capacitance on the pins. The values of C2 and C3 depend on the load
capacitance rating of the crystal that is used, not the 73M2901CE. This load capacitance will typically be
between 15 pF and 27 pF, but usually 18 or 22 pF. Parallel resonant crystals are tuned with a specific
capacitive load and will be within their specifications when this load is used. This rating is the
capacitance measured between the crystal pins including all parasitic capacitances. It is not the values of
the capacitors used. The selection of these capacitors can vary with the layout of the PCB, so do not
assume the values used with the 73M2901CE demo board are correct for all designs.
System noise is the most likely cause of poor Caller ID and low-level receive performance. The lowest
amplitude signals that the modem will need to receive are on the order of 5 mV rms. The Caller ID
receive levels are also very low due to the requirement to have a high (60 k Ω ) AC input impedance while
on hook. Having a 20 dB gain boost during Caller ID reception compensates for this, but if there is
excessive noise, it will also be amplified. Keeping the analog and digital grounds separate helps control
the amount of noise that gets to the receiver input. Dramatic improvements in low-level performance can
be gained by proper layout.
Keep the VCC trace as short as possible. Make the power trace a minimum of 0.5 mm thick. The analog
and digital power and ground should be kept separate for best low receive level performance. Route the
power to the digital pins and bypass capacitors on one net and the analog power and VBG bypass pins
on another net with inductors separating the two. If power planes are used, separate the power and
ground planes so there are separate analog and digital planes for the 73M2901CE.
Keep 0.1 μ F and 3.3 μ F bypass capacitors close to VPD power pins of the device and take other end to
the digital ground.
Keep 0.1 μ F and 10 μ F bypass capacitors close to VPA power pin of the device and directly connect the
other end to analog ground.
Keep all analog signaling away from any high-speed digital circuitry and traces that may be on the board.
Observe the separation of the network and modem side circuitry. Maintain at least ? inch (6 mm)
separation between the two. Do not run power planes under the network side circuitry and maintain the
same spacing for the planes from the network. Use only UL, CSA, or TUV approved components that
cross the isolation barrier or for network protection to assure compliant performance for the DAA.
The transformer used for coupling will have an influence on the values of the components in the DAA
circuitry. The winding resistance, inductances and other characteristics of the transformer affect the
values of the impedance matching components. Make sure you have the transformer manufacturer’s
recommended circuit values when using other transformers. The values can be determined through
simulations, but may still require some adjustment to optimize the design.
Rev. 1.5
7
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